>>>>> "JL" == Jack Lloyd <ll...@randombit.net> writes:
JL> It's also supported in (very very recent) GNU binutils. The sample code Intel provided on that page compiled/assembled correctly here, using binutils-2.21. Noting again that the registers are ordered ax, cx, dx, bx, sp, bp, si, di, then the opcodes are: In 16-bit mode: 0F C7 F0 through 0F C7 F7 randomize 16-bit registers ax through di In 32-bit mode: 66 0F C7 F0 through 66 0F C7 F7 randomize 16-bit registers ax through di 0F C7 F0 through 0F C7 F7 randomize 32-bit registers eax through edi In 64-bit mode: 66 0F C7 F0 through 66 0F C7 F7 randomize 16-bit registers ax through di 0F C7 F0 through 0F C7 F7 randomize 32-bit registers eax through edi 41 0F C7 F0 through 41 0F C7 F7 randomize 32-bit registers r8d through r15d 48 0F C7 F0 through 48 0F C7 F7 randomize 64-bit registers rax through rdi 49 0F C7 F0 through 49 0F C7 F7 randomize 64-bit registers r8 through r15 I confirmed those via objdump(1)'s disassembly. Note the use of prefix octet 0x66 to work on a 16-bit register when in 32-bit or 64-bit modes and the use of 0x48|0x41 (aka 0x49) to access the gp registers r8-r15 as 64-bit registers. It'll be interesting to see what AMD does on this front. -JimC -- James Cloos <cl...@jhcloos.com> OpenPGP: 1024D/ED7DAEA6 _______________________________________________ cryptography mailing list cryptography@randombit.net http://lists.randombit.net/mailman/listinfo/cryptography