In article <1923806e-bdd4-4c7e-9b07-d8937320f...@zoulas.com>,
Christos Zoulas <chris...@zoulas.com> wrote:
>-=-=-=-=-=-
>
>Well, the assembly block is enabled only if we have vis3 instructions:
>
># elif defined(GHASH_ASM_SPARC)
> if (OPENSSL_sparcv9cap_P[0] & SPARCV9_VIS3) {
> gcm_init_vis3(ctx->Htable, ctx->H.u);
> ctx->gmult = gcm_gmult_vis3;
> CTX__GHASH(gcm_ghash_vis3);
> } else {
> gcm_init_4bit(ctx->Htable, ctx->H.u);
> ctx->gmult = gcm_gmult_4bit;
> CTX__GHASH(gcm_ghash_4bit);
> }
>
>What does OPENSSL_sparcv9_cap_P[0] contain.
We are dying in gcm_gmult_4bit because it uses ldx/stx which is only
available on v9... So yes, I have disabled the sparc assembly completely
again as before with __arch64__
christos
