Hi, Apologies for this minor mistake in the implementation of final `ldp` instruction [https://cygwin.com/pipermail/cygwin-patches/2025q2/013833.html]. It caused a regression in pthread-related tests on our testing environment. This patch corrects the register load order and aligns it with the descending stack growth convention in AArch64.
In-lined Patch: >From fc0d02ef009e02d520d934beb9429e64d9b522b4 Mon Sep 17 00:00:00 2001 From: Thirumalai Nagalingam <[email protected]> Date: Wed, 25 Jun 2025 22:23:13 +0530 Subject: [PATCH] Aarch64: Fix register load order in `ldp` in commit f4ba145056dbe99adf4dbe632bec035e006539f8 Adjust register load order in `ldp` instruction from commit f4ba145056dbe99adf4dbe632bec035e006539f8 to reflect descending stack growth. Signed-off-by: Thirumalai Nagalingam <[email protected]> --- winsup/cygwin/create_posix_thread.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/winsup/cygwin/create_posix_thread.cc b/winsup/cygwin/create_posix_thread.cc index 592aaf1a5..845740f2c 100644 --- a/winsup/cygwin/create_posix_thread.cc +++ b/winsup/cygwin/create_posix_thread.cc @@ -104,7 +104,7 @@ pthread_wrapper (PVOID arg) * and calls the thread function with its arg using AArch64 ABI. */ __asm__ __volatile__ ("\n\ mov x19, %[WRAPPER_ARG] // x19 = &wrapper_arg \n\ - ldp x0, x10, [x19, #16] // x0 = stackaddr, x10 = stackbase \n\ + ldp x10, x0, [x19, #24] // x0 = stackaddr, x10 = stackbase \n\ sub sp, x10, %[CYGTLS] // sp = stackbase - (CYGTLS) \n\ mov fp, xzr // clear frame pointer (x29) \n\ mov x1, xzr // x1 = 0 (dwSize) \n\ -- 2.49.0.windows.1 Thanks, Thirumalai Nagalingam
0001-Aarch64-Fix-register-load-order-in-ldp-in-commit-f4b.patch
Description: 0001-Aarch64-Fix-register-load-order-in-ldp-in-commit-f4b.patch
