At 11:06 PM 10/15/03 +0200, Ralf-P. Weinmann wrote: >On Wed, Oct 15, 2003 at 05:14:17PM +0200, Eugen Leitl wrote: >> latest VIA C3 C5P does 1 GHz at 7 W power dissipation, >> has now two hardware RNG engines (and two x86 opcodes to >> read them), and an Advanced Cryptography Engine >> which can do AES (Rijndael128? doesn't say) at >> 12.5 GBit/s rate. > >Look at the PadLock ACE programming guide [1]. Only seems to support Rijndael >with a block size of 128 bits (= AES); it allows both key scheduling in
>hardware and in software, the latter allowing you to have your own custom >key schedule. It also allows you to increase the number of rounds if you >think Rijndael-128's security margins are too low. Props to the VIA engineers >for both the customizability. Which is unlikely to be used, at it would be incompatible with everything else. The "customizability" is likely a flexibility they built for their own (debug, architectural) reasons and decided to expose to users. What they need is a USB or Ethernet interface to catch up to others. However the attraction of a relatively fast x86 (vs say a 100 Mhz MIPS or ARM) might offset this lack of integration for some designs. Am surprised not to see a little DES core stuffed into the spare space on the die, but kinda nostalgically pleased to see DES's EOL. RIP. >The errate are funny as well. Looks like the I found the following lexical rule mildly amusing, because I have seen the same thing added to military docs to make them politically correct (he -> he or she) without editing the whole damn thing. "NOTE: Throughout this document, a reference to encryption generally means both encryption and decryption."
