Hi
I have tried according to CODE REFERENCE, the result is as follows:
The test case is:
0)power on board
1)start one process to copy large datas to hard disk
2)start another process to change PINMUX0 to enable EMIF, and then return to ATA
3)do 2) about 40 times
4)test over, power down.
a)in PIO mode:
I do the test case 5 times, 4 times is ok, one is failed.
The failed information is:
BUG: scheduling while atomic: sh/0x00010105/917
caller is schedule+0xec/0x12c
b)in DMA mode:
I do the test case 2 times, all failed.
hda: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
ide: failed opcode was: unknown
hda: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
ide: failed opcode was: unknown
hda: dma_intr: status=0xd0 { Busy }
ide: failed opcode was: unknown
hda: DMA disabled
so, there maybe some issues to solve.
chendh
------------------------------
Message: 2
Date: Thu, 16 Nov 2006 16:33:29 -0500
From: "Steve Spano" <[EMAIL PROTECTED]>
Subject: ### USING ATA AND EMIF - CODE REFERENCE
To: <davinci-linux-open-source@linux.davincidsp.com>
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset="us-ascii"
Hi
Found a few minor issues when stressing the ATA + EMIF together
So here is what I did to work around the problems
1. Using the hdparm utility (hdparm -d 0 -r 0 -p 0 /dev/had) --> to put
the hdd into a non-dma, slow mode
2. use this sequence shown below to swap between HDD and EMIF
// read current state if PINMUX0
register
lock_kernel();
local_irq_save(flags); // key here is
to stop the scheduler for switching to some ATA related task
pmr=__REG(DAVINCI_SYSTEM_MODULE_BASE);
tpmr=pmr;
tpmr&=~(1<<17); // restore normal
operations to EMIF (i.e. shut off ATA mode)
__REG(DAVINCI_SYSTEM_MODULE_BASE)=tpmr;
__REG(DAVINCI_ASYNC_EMIF_CNTRL_BASE+0x14)=0x3FFFFFD; // 16-bit slow bus on
CS3
for (delay=0;delay<100;delay++)
asm("nop"); // timing for back-to-back on the CPLD
__MWR(MDIC_REG_BASE+8)=1; // issue hw
reset
for (delay=0;delay<100000;delay++)
asm("nop"); // timing for back-to-back on the CPLD
__MWR(MDIC_REG_BASE+8)=0; // release hw
reset
for (delay=0;delay<100000;delay++)
asm("nop"); // timing for back-to-back on the CPLD
__MWR(MDIC_REG_BASE+8)=2; // allow clock
to run again
for (delay=0;delay<100000;delay++)
asm("nop"); // timing for back-to-back on the CPLD
__REG(DAVINCI_SYSTEM_MODULE_BASE+0x14)=tpmra; // back to the way we were
__REG(DAVINCI_SYSTEM_MODULE_BASE)=pmr;
// back to the way we were
local_irq_restore(flags);
unlock_kernel();
for (delay=0;delay<100000;delay++)
asm("nop");
break;
Steve Spano, President
Finger Lakes Engineering
607-277-1614
www.fl-eng.com
[EMAIL PROTECTED]
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