When codecs share resources, they must be configured into the same 'group', like this: Server.algs = [ {name: "viddec_copy", mod: VIDDEC_COPY, threadAttrs: { stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 0, }, {name: "videnc_copy", mod: VIDENC_COPY, threadAttrs: { stackMemId: 0, priority: Server.MINPRI + 2}, groupId : 0, } ]; You might consider posting the entire server config script so we can sanity check it, and see if anything else jumps out. Chris
________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] com] On Behalf Of X. Zhou Sent: Thursday, February 15, 2007 5:37 AM To: davinci-linux-open-source@linux.davincidsp.com Subject: DMA channels sharing between multiple algorithms Hi, everyone, I encounterer a very weird problem related to DMA which needs your help. I use the DVSDK software architecure to develop a H.264 video codec on the EVM6446 board. At dsp side, there are 2 algorithms, one is encoder, which use 8 QDMA channels and totally 30 param entryes during each process loop, the other is decoder, which use also 8 QDMA channels and totally 16 param entryes) during each process loop, And I configure the server just like the following: ............. DMAN3.qdmaPaRamBase = 0x01C04000; DMAN3.maxPaRamEntries = 128; DMAN3.paRamBaseIndex = 64; DMAN3.numPaRamEntries = 64; DMAN3.maxQdmaChannels = 8; DMAN3.numQdmaChannels = 8; DMAN3.qdmaChannels = [0,1,2,3,4,5,6,7]; DMAN3.numTccGroup[0] = 8; DMAN3.numPaRamGroup[0] = 64; DMAN3.tccAllocationMaskH = 0xffffffff; DMAN3.tccAllocationMaskL = 0x00000000; DMAN3.heapInternal = "L1DSRAM_HEAPLABEL"; DMAN3.heapExternal = "DDR_HEAPLABEL"; DMAN3.idma3Internal = true; ............. The main loop of my application is just like the following: henc = VIDENC_create(hCE, encoder_name, &encparams); hdec = VIDENC_create(hCE, decoder_name, &decparams); while ( i < frameNum ) { ....... if ( encoder_enable_flag ) { status = VIDENC_process(henc, &enc_inbuf_desc, &enc_outbuf_desc, &enc_inargs, &enc_outargs); } ....... if ( decoder_enable_flag ) { status = VIDDEC_process(hdec, &dec_inbuf_desc, &dec_outbuf_desc, &dec_inargs, &dec_outargs); } ....... } Now the problem is: (1) If I enable both encoder and decoder(i.e., set encoder_enable_flag and decoder_enable_flag to be 1), sometimes decoder's decoded frames is not consistent to the standard decoded frames. But if i only enable decoder only (i.e., encoder_enable_flag = 1 and decoder_enable_flag = 1), the decoder works perfectly always. (2) I replace all the DMA transfer opeations in decoder with memcpy() functions, and then repeat the steps in (1), the decoder does work . So i doubt this problem maybe is caused by the DMA configuration and DMA channels sharing between 2 algorithms. I have checked all the DMA configurations in both my encoder and decoder, for example, at the entry point and exit point of each process call, make sure all the QDMA channels has been in done status, and activate ( at the entry point) / deacitivate ( at the exit point) them. And I am sure that the DMA configuration is correct, and no memory out-of-range accesses exit. have i missed something about DMA channels sharing between multiple algorithms? Who can give me any clue about it? ZhouX This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
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