If you're using Codec Engine (which version?), can you also provide your
DSP Server's .cfg script and the generated .map file (probably in the
server's generated package/cfg/* directory)?
I'd like to understand what codecs are in the system, and what resources
they may be sharing (e.g. DSKT2 scratch config).
Also, are any of the codecs using DMA, and if so, are they using ACPY3?
Chris
________________________________
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On
Behalf Of yang shaobo
Sent: Thursday, October 25, 2007 3:10 AM
To: [email protected]
Subject: The Use of L1DSRAM
The Use of L1DSRAM
Hi all,
I have a proleme about the use of L1DSRAM.I find that not all
the L1DSRAM can be used by our algrithom.
Only about 50k of L1DSRAM can be used.When I increase the use of
L1DSRAM,for example ,if I set the heapsize to be 62 KByte ,my
application corrupted.
I wonder whether my configuration of tcf file is incorrect or
some other configuration is wrong.
The following is part of my tcf file:
########################################################################
#####################################
var device_regs = {
l2Mode: "64k"
};
var params = {
clockRate: 567,
catalogName: "ti.catalog.c6000",
deviceName: "DM6446",
regs: device_regs,
mem: mem_ext
};
/*
* Customize generic platform with parameters specified above.
*/
utils.loadPlatform("ti.platforms.generic", params);
/*
========================================================================
===
* Enable heaps and tasks
*
========================================================================
===
*/
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);
prog.module("GBL").C64PLUSCONFIGURE = true;
prog.module("GBL").C64PLUSL1DCFG = "16k"; // changed from
default of 32k
/* increase the size of the L1DSRAM by 16K because L1 Cache
size has been
* reduced by 16K
*/
bios.L1DSRAM.len += 0x4000;
/*
========================================================================
===
* Create heaps in memory segments that are to have heap
*
========================================================================
===
*/
bios.DDR.createHeap = true;
bios.DDR.heapSize = 0x20000; // 512K
bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len;
bios.L1DSRAM.createHeap = true;
bios.L1DSRAM.enableHeapLabel = true;
bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP");
bios.L1DSRAM.heapSize = 0xF800; // The
change is here!!!!!!!
/*
========================================================================
===
* GBL
*
========================================================================
===
*/
/* set MAR register to cache external memory
0x80000000-0x8FFFFFFF */
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;
prog.module("GBL").ENABLEALLTRC = false;
prog.module("GBL").PROCID = 0;
/* user init function calls Link's HAL initialization */
prog.module("GBL").CALLUSERINITFXN = 1;
prog.module("GBL").USERINITFXN = prog.extern("HAL_init");
/*
========================================================================
===
* Enable cpu load measurement TODO: this should be in OSAL!!!
*
========================================================================
===
*/
var cpuLoad = prog.module("IDL").create("Global_cpuLoad");
cpuLoad.fxn = prog.extern("LOAD_idlefxn");
cpuLoad.calibration = true;
/*
========================================================================
===
* MEM : startup and SWI stack size
*
========================================================================
===
*/
prog.module("MEM").STACKSIZE = 0x1000;
/*
========================================================================
===
* Global Settings
*
========================================================================
===
*/
prog.module("MEM").ARGSSIZE = 256;
/*
========================================================================
===
* Enable MSGQ and POOL Managers
*
========================================================================
===
*/
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;
/*
========================================================================
===
* Set all code and data sections to use DDR
*
========================================================================
===
*/
bios.setMemCodeSections (prog, bios.DDR);
bios.setMemDataNoHeapSections (prog, bios.DDR);
bios.setMemDataHeapSections (prog, bios.DDR);
/*
========================================================================
===
* MEM : Global
*
========================================================================
===
*/
prog.module("MEM").BIOSOBJSEG = bios.DDR;
prog.module("MEM").MALLOCSEG = bios.DDR;
/*
========================================================================
===
* add by Sleepy Boy
* change the physical position of system stack, .far
.switch
*
========================================================================
===
*/
prog.module("MEM").STACKSEG = bios.L1DSRAM;
prog.module("MEM").BSSSEG = bios.L1DSRAM;
prog.module("MEM").ARGSSEG = bios.DDR;
prog.module("MEM").SWITCHSEG = bios.DDR ;
prog.module("MEM").CINITSEG = bios.DDR;
prog.module("MEM").PINITSEG = bios.DDR;
prog.module("MEM").CONSTSEG = bios.DDR;
prog.module("MEM").DATASEG = bios.L1DSRAM;
prog.module ("MEM").CIOSEG = bios.L1DSRAM;
prog.module("MEM").GBLINITSEG = bios.DDR;
prog.module("MEM").TRCDATASEG = bios.DDR;
prog.module("MEM").SYSDATASEG = bios.L1DSRAM;
prog.module("MEM").OBJSEG = bios.L1DSRAM;
/*
========================================================================
===
* TSK : Global
*
========================================================================
===
*/
prog.module("TSK").STACKSEG = bios.DDR;
/*
========================================================================
===
* Generate configuration files...
*
========================================================================
===
*/
if (config.hasReportedError == false) {
prog.gen();
}
########################################################################
#####################################
Best Regards,
Sleepy Boy.
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