Dear all
I am porting XVID's mpeg4 codec to my DAVINCI platform(dm6446,with
64M DDR2).First,I build the xvid_core src to xvid_core.lib in CCS with
no optimized, then copy it to "./servers/all_codecs/" and add a line
"-l xvid_core.lib" to link.cmd. Build my project and run the app
everything is OK! The encode and decode result are all correct. But
when I optimized some functions in the xvid_core src useing assembly
language, copy the new "xvid_core.lib" to my project and rebuild the
project (make clean;make ). Run the app, the DSP was often halted or
reset sometimes. Following are my config file.
DSPLINK config file "CFG_Davinci.TXT":
[DRIVER]
NAME | S | DSP/BIOS LINK # Driver name
COMPONENTS | N | 2 # Configuration being used
QUEUELENGTH | N | 16 # Queue length for the CHNL driver
NUMDSPS | N | 1 # Number of DSPs in the system
NUMMEMTABLES | N | 1 # Number of memory tables
NUMIPSTABLE | N | 1 # Number of IPS tables
NUMPOOLS | N | 1 # Number of POOLs
NUMDATATABLES | N | 1 # Number of data tables
MAXMSGQS | N | 16 # Maximum MSGQs that can be opened
NUMMQTS | N | 1 # Number of MQTs
PROBERTCID | N | 3 # Real Time Clock ID for PROBE
PROBEINTID | N | 33 # Interrupt ID for PROBE
LOG_OBJECT | A | trace # Log object for logging
[/DRIVER]
[GPP]
NAME | S | ARM9 # Name of the GPP
[/GPP]
[DSP0]
NAME | S | Gem # Name of the DSP
ARCHITECTURE | E | DspArch_C64x # DSP architecture
INTERFACE | A | DAVINCI_Interface # DSP interface table
LOADER | A | COFF_Interface # Loader interface table
LOADSYMBOLS | B | FALSE # Load symbols from DSP executable
AUTOSTART | B | FALSE # Autostart the DSP (Not supported)
DOPOWERCTRL | B | TRUE # Link does the Power Ctrl of DSP.
EXECUTABLE | S | DEFAULT.OUT # Executable for autostart
RESUMEADDR | H | 0x83F00020 # Resume address
RESETVECTOR | H | 0x83F00000 # Reset Vector for the DSP
RESETCODESIZE | H | 0x80 # Size of code at DSP Reset Vector
MADUSIZE | N | 1 # DSP Minimum Addressable Data Unit
ENDIAN | N | 3 # DSP Endianism
MEMENTRIES | N | 5 # Number of entries in memory table
MEMTABLEID | N | 0 # ID of the memory table used
LINKDRVID | N | 0 # ID of the link driver used
NUMDATADRV | N | 1 # Number of data drivers supported
DATATABLEID | N | 0 # ID of the data driver table
MQTID | N | 0 # ID of the MQT
LOG_OBJECT | A | trace # Log object for logging
[/DSP0]
[MEMTABLE0]
[0]
ENTRY | N | 0 # Entry number
ABBR | S | DSPLINKMEM # Abbreviation of the table name
ADDRDSPVIRTUAL | H | 0x83e00000 # DSP virtual address
ADDRPHYSICAL | H | 0x83e00000 # Physical address
SIZE | H | 0x100000 # Size of the memory region
MAPINGPP | B | TRUE # Map in GPP address space?
[/0]
[1]
ENTRY | N | 1 # Entry number
ABBR | S | RESETCTRL # Abbreviation of the table name
ADDRDSPVIRTUAL | H | 0x83F00000 # DSP virtual address
ADDRPHYSICAL | H | 0x83F00000 # Physical address
SIZE | H | 0x00000080 # Size of the memory region
MAPINGPP | B | TRUE # Map in GPP address space?
[/1]
[2]
ENTRY | N | 2 # Entry number
ABBR | S | DDR # Abbreviation of the table name
ADDRDSPVIRTUAL | H | 0x83F00080 # DSP virtual address
ADDRPHYSICAL | H | 0x83F00080 # Physical address
SIZE | H | 0x0FFF80 # Size of the memory region
MAPINGPP | B | TRUE # Map in GPP address space?
[/2]
[3]
ENTRY | N | 3 # Entry number
ABBR | S | DSPIRAM # Abbreviation of the table name
ADDRDSPVIRTUAL | H | 0x11800000 # DSP virtual address
ADDRPHYSICAL | H | 0x11800000 # Physical address
SIZE | H | 0x10000 # Size of the memory region
MAPINGPP | B | TRUE # Map in GPP address space?
[/3]
[4]
ENTRY | N | 4 # Entry number
ABBR | S | DSPL1DRAM # Abbreviation of the table name
ADDRDSPVIRTUAL | H | 0x11F04000 # DSP virtual address
ADDRPHYSICAL | H | 0x11F04000 # Physical address
SIZE | H | 0xC000 # Size of the memory region
MAPINGPP | B | TRUE # Map in GPP address space?
[/4]
[/MEMTABLE0]
[POOLS]
[0]
NAME | S | SMA # Name of the pool
ABBR | S | SMAPOOL # Abbreviation of the pool name
FXN_INITIALIZE | A | SMAPOOL_Initialize # Initialize function for the pool
FXN_FINALIZE | A | SMAPOOL_Finalize # Finalize function for the pool
INTERFACE | A | SMAPOOL_Interface # Pool interface table
DSPID | N | 0 # DSP ID used by the pool
(-1 if not needed)
MEMENTRY | N | 0 # Memory entry ID (-1 if not needed)
POOLSIZE | H | 0x70000 # Size of the pool (-1 if not needed)
ARGUMENT1 | H | 0x0 # First Pool-specific argument
ARGUMENT2 | H | 0x0 # Second Pool-specific argument
[/0]
[/POOLS]
[LINKDRV0]
NAME | S | SHMDRV # Name of the link driver
ABBR | S | SHMDRV # Abbreviation of the link
driver name
INTERFACE | A | SHMDRV_Interface # Link driver interface table
MEMENTRY | N | 0 # Memory entry ID (-1 if not needed)
SIZE | M | SHMDRV_CTRL_SIZE # Memory size needed from
the mem entry
IPSENTRIES | N | 1 # Number of IPS supported
IPSTABLEID | N | 0 # ID of the IPS table used
[/LINKDRV0]
[IPSTABLE0]
[0]
NAME | S | SHMIPS # Name of the
Inter-Processor-Signaling component
ABBR | S | SHMIPS # Abbreviation of the IPS name
FXN_INITIALIZE | A | SHMIPS_Initialize # Initialize function for the IPS
FXN_FINALIZE | A | SHMIPS_Finalize # Finalize function for the IPS
QUEUEPERCHANNEL | N | 1 # Number of queued buffers
per data channel
SIZE | M | SHMIPS_CTRL_SIZE # Memory size needed from
the mem entry
IRPSIZE | M | SHMIPS_IRP_SIZE # Size of each IO Request
Packet for data transfer
MEMENTRY | N | 0 # Memory entry ID (-1 if not needed)
ARGUMENT1 | N | 0 # First IPS-specific argument
ARGUMENT2 | N | 0 # Second IPS-specific argument
[/0]
[/IPSTABLE0]
[MQT0]
NAME | S | ZCPYMQT # Name of the Message Queue Transport
ABBR | S | ZCPYMQT # Abbreviation of the MQT name
INTERFACE | A | ZCPYMQT_Interface # MQT Interface table
MEMENTRY | N | -1 # Memory entry ID (-1 if not needed)
MAXMSGSIZE | N | -1 # Maximum message size
supported (-1 if no limit)
SIZE | H | 0x0 # Memory size needed from
the mem entry
ARGUMENT1 | H | 0x0 # First MQT-specific argument
ARGUMENT2 | H | 0x0 # Second MQT-specific argument
[/MQT0]
[DATADRV0]
[0]
NAME | S | ZCPYDATA # Name of the HPI driver
ABBR | S | ZCPYDATA # Abbreviation
BASECHANNELID | N | 0 # Base channel id for the driver
NUMCHANNELS | N | 16 # Number of channels supported
MAXBUFSIZE | N | 16384 # Maximum size of buffer supported
INTERFACE | A | ZCPYDATA_Interface # Data transfer interface table
MEMENTRY | N | 0 # Memory entry ID (-1 if not needed)
POOLID | N | 0 # Pool id for allocating buffers
SIZE | M | ZCPYDATA_CTRL_SIZE # Size of the control structure
ARGUMENT1 | H | 0x0 # First data transfer
driver specific argument
ARGUMENT2 | H | 0x0 # Second data transfer
driver specific argument
[/0]
[/DATADRV0]
[LOG]
GD_MSGQ_PUT | B | FALSE # GPP->DSP MSG Transfer -
MSGQ_Put call.
GD_MSGQ_SND | B | FALSE # GPP->DSP MSG Transfer -
GPP sends interrupt.
GD_MSGQ_ISR | B | FALSE # GPP->DSP MSG Transfer -
DSP receives interrupt.
GD_MSGQ_QUE | B | FALSE # GPP->DSP MSG Transfer -
Message queued at DSP.
DG_MSGQ_PUT | B | FALSE # DSP->GPP MSG Transfer -
MSGQ_Put call.
DG_MSGQ_SND | B | FALSE # DSP->GPP MSG Transfer -
DSP sends interrupt.
DG_MSGQ_ISR | B | FALSE # DSP->GPP MSG Transfer -
GPP receives interrupt.
DG_MSGQ_QUE | B | FALSE # DSP->GPP MSG Transfer -
Message queued at GPP.
GD_CHNL_I_START | B | FALSE # GPP->DSP CHNL Transfer -
Entring inside ISSUE call.
GD_CHNL_I_QUE | B | FALSE # GPP->DSP CHNL Transfer -
Buffer is queued in internal structure on GPP.
GD_CHNL_I_COMPLETE | B | FALSE # GPP->DSP CHNL Transfer -
ISSUE call completed.
GD_CHNL_XFER_START | B | FALSE # GPP->DSP CHNL Transfer -
Initiating a buffer transfer by GPP.
GD_CHNL_XFER_PROCESSING | B | FALSE # GPP->DSP CHNL Transfer -
Actual transfer of buffer is going to take place.
GD_CHNL_XFER_COMPLETE | B | FALSE # GPP->DSP CHNL Transfer -
Buffer transfer is complete.
GD_CHNL_R_START | B | FALSE # GPP->DSP CHNL Transfer -
Entring RECLAIM call.
GD_CHNL_R_PEND | B | FALSE # GPP->DSP CHNL Transfer -
Wait on a semaphore.
GD_CHNL_R_POST | B | FALSE # GPP->DSP CHNL Transfer -
posting the Semaphore.
GD_CHNL_R_COMPLETE | B | FALSE # GPP->DSP CHNL Transfer -
RECLAIM call completed.
DG_CHNL_I_QUE | B | FALSE # DSP->GPP CHNL Transfer -
Buffer is queued in internal structure on DSP.
DG_CHNL_XFER_START | B | FALSE # DSP->GPP CHNL Transfer -
Initiating a buffer transfer by DSP.
DG_CHNL_XFER_PROCESSING | B | FALSE # DSP->GPP CHNL Transfer -
Actual transfer of buffer is going to take place.
DG_CHNL_XFER_COMPLETE | B | FALSE # DSP->GPP CHNL Transfer -
Buffer transfer is complete.
DG_CHNL_R_PEND | B | FALSE # DSP->GPP CHNL Transfer -
Wait on a semaphore.
DG_CHNL_R_POST | B | FALSE # DSP->GPP CHNL Transfer -
posting the Semaphore.
MSG_ID_R_START | N | 10 # MSG ID range: lower limit
MSG_ID_R_END | N | 20 # MSG ID range: upper limit
[/LOG]
servers config file "all.tcf":
/*
* Setup platform-specific memory map:
*/
var mem_ext = [
{
comment: "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
name: "DDRALGHEAP",
base: 0x82400000, // 28MB
len: 0x01600000, // 122MB
space: "code/data"
},
{
comment: "DDR: off-chip memory for application code and data",
name: "DDR",
base: 0x83a00000, // 250MB
len: 0x00400000, // 4MB
space: "code/data"
},
{
comment: "DSPLINK: off-chip memory reserved for DSPLINK code and data",
name: "DSPLINKMEM",
base: 0x83e00000, // 254MB
len: 0x00100000, // 1MB
space: "code/data"
},
{
comment: "RESET_VECTOR: off-chip memory for the reset vector table",
name: "RESET_VECTOR",
base: 0x83f00000,
len: 0x00000080,
space: "code/data"
},
];
/*
* Internal memory partitioning
*
* On the left in the diagram below is the layout of internal memory
* available on DM6446 for data caching and as RAM; on the right is the
* diagram showing how this configuration file partitions the available
* 64k+80k of memory. (The 32K for program cache is not affected by this
* configuration.) Please find more specifics on how the configuration is
* done further below.
*
*
* Physical internal memory on DM6446 Default partitioning in this .tcf
*
* |//////////| |//////////|
* 0x11800000 +----------+ 0x11800000 +----------+
* | L2Cache | | |
* | and/or | 64k | L2 Cache | 64k
* | IRAM | | |
* | | | |
* 0x11810000 +----------+ 0x11810000 +----------+
* |//////////| |//////////|
* : : : :
* |//////////| |//////////|
* 0x11F04000 +----------+ 0x11F04000 +----------+
* | | | |
* | L1DSRAM | 48k | L1DSRAM |
* | | | | 64k
* 0x11F10000 +- - - - - + | |
* |L1Cache or| 32k +- - - - - +
* |more L1DSR| 0x11F14000 | L1 cache | 16k
* 0x11F18000 +----------+ 0x11F18000 +----------+
* |//////////| |//////////|
*/
/*
* Specify the L2 CACHE memory setting. This value indicates how the physical
* internal memory of size 64K starting at 0x11800000 will be split between
* L2 cache and a general-purpose internal memory segment IRAM. The options
* are:
* l2Mode: "0k" -- IRAM is 64K long, starts at 0x11800000; no L2 cache
* l2Mode: "32k" -- IRAM is 32K long, starts at 0x11800000; L2 cache is
* 32K long, starts at 0x11808000
* l2Mode: "64k" -- no IRAM; L2 cache is 64k long, starts at 0x11800000
*/
var device_regs = {
l2Mode: "64k"
};
var params = {
clockRate: 567,
catalogName: "ti.catalog.c6000",
deviceName: "DM6446",
regs: device_regs,
mem: mem_ext
};
/*
* Customize generic platform with parameters specified above.
*/
utils.loadPlatform("ti.platforms.generic", params);
/* ===========================================================================
* Enable heaps and tasks
* ===========================================================================
*/
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);
/* ===========================================================================
* Configure L1 cache and L1DSRAM segment
*
* In addition to the 64K at address 0x11800000, the DM6446 device has another
* 48K of physical memory at 0x11F04000 available as internal RAM,
* called the "L1DSRAM" segment in BIOS, and it has another adjacent 32K
* at 0x11F10000 that can either be used entirely for L1 cache,
* or split between L1 cache and more internal memory.
*
* The 80K segment (48K + 32K) starts at 0x11F04000. When powered on, the
* device uses the upper 32K for L1 cache entirely, so BIOS by default defines
* the L1DSRAM segment to be 48K long and does not change the cache.
*
* We can change the default behavior, by shrinking the L1 cache and adding
* the extra space to L1DSRAM. We can set the L1 cache to be 32K (the default)
* or 16K, 8K, 4K, or 0K. The corresponding L1DSRAM sizes then are 48K (the
* default), or 64K, 72K, 76K, or 80K.
*
* The L1DSRAM segment always starts at 0x11F04000.
* ===========================================================================
*/
prog.module("GBL").C64PLUSCONFIGURE = true;
prog.module("GBL").C64PLUSL1DCFG = "16k"; // changed from default of 32k
/* increase the size of the L1DSRAM by 16K because L1 Cache size has been
* reduced by 16K
*/
bios.L1DSRAM.len += 0x4000;
/* ===========================================================================
* Create heaps in memory segments that are to have heap
* ===========================================================================
*/
bios.DDR.createHeap = true;
bios.DDR.heapSize = 0x20000; //2M
bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len;
bios.L1DSRAM.createHeap = true;
bios.L1DSRAM.enableHeapLabel = true;
bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP");
bios.L1DSRAM.heapSize = 0x8000;
/* ===========================================================================
* GBL
* ===========================================================================
*/
/* set MAR register to cache external memory 0x80000000-0x8FFFFFFF */
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;
prog.module("GBL").ENABLEALLTRC = false;
prog.module("GBL").PROCID = 0;
/* user init function calls Link's HAL initialization */
prog.module("GBL").CALLUSERINITFXN = 1;
prog.module("GBL").USERINITFXN = prog.extern("HAL_init");
/* ===========================================================================
* Enable cpu load measurement TODO: this should be in OSAL!!!
* ===========================================================================
*/
var cpuLoad = prog.module("IDL").create("Global_cpuLoad");
cpuLoad.fxn = prog.extern("LOAD_idlefxn");
cpuLoad.calibration = true;
/* ===========================================================================
* MEM : startup and SWI stack size
* ===========================================================================
*/
prog.module("MEM").STACKSIZE = 0x1000;
/* ===========================================================================
* Global Settings
* ===========================================================================
*/
prog.module("MEM").ARGSSIZE = 256;
/* ===========================================================================
* Enable MSGQ and POOL Managers
* ===========================================================================
*/
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;
/* ===========================================================================
* Set all code and data sections to use DDR
* ===========================================================================
*/
bios.setMemCodeSections (prog, bios.DDR);
bios.setMemDataNoHeapSections (prog, bios.DDR);
bios.setMemDataHeapSections (prog, bios.DDR);
/*bios.setMemDataHeapSections (prog, bios.DDRALGHEAP);*/
/* ===========================================================================
* MEM : Global
* ===========================================================================
*/
prog.module("MEM").BIOSOBJSEG = bios.DDR;
/*prog.module("MEM").MALLOCSEG = bios.DDR;fix mp4 bug by zjj*/
prog.module("MEM").MALLOCSEG = bios.DDRALGHEAP;
/* ===========================================================================
* TSK : Global
* ===========================================================================
*/
/*prog.module("TSK").STACKSEG = bios.DDR; fix mp4 problem by zjj,2007.11.16*/
prog.module("TSK").STACKSEG = bios.DDRALGHEAP;
/* ===========================================================================
* Generate configuration files...
* ===========================================================================
*/
if (config.hasReportedError == false) {
bios.GBL.C64PLUSL1DCFG = "8k";
bios.MEM.instance("CACHE_L2").space = "code/data";
bios.MEM.instance("DDR").enableHeapLabel = 1;
bios.MEM.instance("DDR").heapLabel = prog.extern("DDR", "asm");
bios.MEM.instance("L1DSRAM").createHeap = 0;
bios.MEM.instance("L1DSRAM").space = "code/data";
bios.POOL.ENABLEPOOL = 0;
bios.MEM.instance("DDR").enableHeapLabel = 0;
bios.MEM.instance("L1DSRAM").createHeap = 1;
bios.MEM.instance("L1DSRAM").enableHeapLabel = 1;
bios.MEM.instance("L1DSRAM").heapLabel = prog.extern("L1DHEAP", "asm");
bios.MEM.instance("L1DSRAM").heapLabel = prog.extern("L1DHEAP");
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
prog.gen();
}
Part of my dsp0trace
......
@0x0050ae17:[T:0x83aff17c] ti.sdo.ce.video.VIDDEC - VIDDEC_process>
Enter (handle=0x83aff0c0, inBufs=0x82bca524, outBufs=0x82bca530,
inArgs=0x83e04938, outArgs=0x83e04944)
@0x0050ae79:[T:0x83aff17c] CV - VISA_enter(visa=0x83aff0c0): algHandle
= 0x83aff0d8
@0x0050aeaa:[T:0x83aff17c] ti.sdo.ce.osal.AlgMem - AlgMem_activate>
Enter(handle=0x83aff0d8)
@0x0050aedd:[T:0x83aff17c] ti.sdo.ce.osal.AlgMem - AlgMem_activate> return
@0x0050af04:[T:0x83aff17c] codecs.mpeg4dec -
MPEG4DEC_PROBA_process(0x82bb3ac0, 0x82bca530, 0x83e04944, 0x0,
0x82bca530)
@0x00519990:[T:0x83aff17c] codecs.mpeg4dec - MPEG4DEC_PROBA_process>
processed 2382 bytes.type:2
@0x005199d7:[T:0x83aff17c] codecs.mpeg4dec - MPEG4DEC_PROBA_process>
Total processed 2382 bytes.
@0x00519a0f:[T:0x83aff17c] CV - VISA_exit(visa=0x83aff0c0): algHandle
= 0x83aff0d8
@0x00519a41:[T:0x83aff17c] ti.sdo.ce.osal.AlgMem - AlgMem_deactivate>
Enter(handle=0x83aff0d8)
@0x00519a75:[T:0x83aff17c] ti.sdo.ce.osal.AlgMem - AlgMem_deactivate> return
@0x00519a9c:[T:0x83aff17c] ti.sdo.ce.video.VIDDEC - VIDDEC_process>
Exit (handle=0x83aff0c0, retVal=0x0)
@0x00519ad6:[T:0x83aff17c] OM - Memory_cacheWbInv>
Enter(addr=0x82100000, sizeInBytes=460800)
@0x00519cff:[T:0x83aff17c] OM - Memory_cacheWbInv> return
@0x00519d22:[T:0x83aff17c] CN - NODE> returned from
call(algHandle=0x83aff0c0, msg=0x83e04800); messageId=0x00020130
@0x00519daf:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x00519dde:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x0051b4b1:[T:0x83afe9a4] CR - processRmsCmd(0x83e01828, 4056): cmd = 4
@0x0051b4e0:[T:0x83afe9a4] OG - Global_getCpuLoad: window = 0x4536c00, load = 13
@0x0051bd6e:[T:0x83afe9a4] CR - processRmsCmd(0x83e01828, 4056): cmd = 3
@0x0051bd9b:[T:0x83afe9a4] OM - Memory_segStat(0x0, 0x82400784)
@0x0051bdc8:[T:0x83afe9a4] OM - Memory_segStat(0x1, 0x82400784)
@0x0051bdf1:[T:0x83afe9a4] OM - Memory_segStat(0x2, 0x82400784)
@0x0051be17:[T:0x83afe9a4] OM - Memory_segStat(0x3, 0x82400784)
@0x0051be5b:[T:0x83afe9a4] CR - RMS: stack size = 2048, stack used = 1291(64%)
@0x00522b18:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x00522b43:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x005501e1:[T:0x00000000] servers.all_codecs - main> Welcome to DSP
server's main. (argc=2, argv[0]='./all.x64P', argv[1]='*=01234567')
@0x005cfe79:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x005cfea8:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x0067f565:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x0067f590:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x0072f02f:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x0072f059:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x007deb45:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x007deb6f:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x0088e25c:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x0088e286:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x0093e207:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x0093e232:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x009ed630:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x009ed65b:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x00a9cf9f:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x00a9cfca:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x00b4ca04:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
@0x00b4ca2e:[T:0x83afe9a4] CR - remote time = 0x0, trace buffer size = 4032
@0x00bfc3a4:[T:0x83afe9a4] CR - processRmsCmd(0x83e02828, 4056): cmd = 5
......
End of my armtrace
......
@0x043af533:[T:0x411b9b60] OC - Comm_put> return (0)
@0x043af601:[T:0x411b9b60] OC - Comm_get> Enter(msgqQueue=0x10001,
msg=0x411b9590, timeout=-1)
@0x043af6a7:[T:0x411b9b60] OC - Comm_get> return (0)
@0x043af72c:[T:0x411b9b60] CE - Engine_fwriteTrace> got 149 chars
@0x43af3f6 (0 still avail, max: 32744, lost: 0)
@0x043fae34:[T:0x411b9b60] CE - Engine_fwriteTrace(0x268c8, '', 0x26458)
@0x043faf01:[T:0x411b9b60] CE - Engine_fwriteTrace(): requesting DSP
trace @0x43faef2 ...
@0x043faf87:[T:0x411b9b60] OC - Comm_put> Enter(msgqQueue=0x0, msg=0x4094b800)
@0x043fb02e:[T:0x411b9b60] OC - Comm_put> return (0)
@0x043fb0e9:[T:0x411b9b60] OC - Comm_get> Enter(msgqQueue=0x10001,
msg=0x411b9590, timeout=-1)
@0x043fb185:[T:0x411b9b60] OC - Comm_get> return (0)
@0x043fb204:[T:0x411b9b60] CE - Engine_fwriteTrace> got 149 chars
@0x43faef2 (0 still avail, max: 32744, lost: 0)
@0x04446958:[T:0x411b9b60] CE - Engine_fwriteTrace(0x268c8, '', 0x26458)
@0x04446a6f:[T:0x411b9b60] CE - Engine_fwriteTrace(): requesting DSP
trace @0x4446a5d ...
@0x04446afe:[T:0x411b9b60] OC - Comm_put> Enter(msgqQueue=0x0, msg=0x4094b800)
@0x04446bab:[T:0x411b9b60] OC - Comm_put> return (0)
@0x04446c81:[T:0x411b9b60] OC - Comm_get> Enter(msgqQueue=0x10001,
msg=0x411b9590, timeout=-1)
@0x04446d26:[T:0x411b9b60] OC - Comm_get> return (0)
@0x04446da8:[T:0x411b9b60] CE - Engine_fwriteTrace> got 149 chars
@0x4446a5d (0 still avail, max: 32744, lost: 0)
@0x04492413:[T:0x411b9b60] CE - Engine_fwriteTrace(0x268c8, '', 0x26458)
@0x044924df:[T:0x411b9b60] CE - Engine_fwriteTrace(): requesting DSP
trace @0x44924d1 ...
@0x04492565:[T:0x411b9b60] OC - Comm_put> Enter(msgqQueue=0x0, msg=0x4094b800)
@0x04492610:[T:0x411b9b60] OC - Comm_put> return (0)
@0x044926da:[T:0x411b9b60] OC - Comm_get> Enter(msgqQueue=0x10001,
msg=0x411b9590, timeout=-1)
@0x04492781:[T:0x411b9b60] OC - Comm_get> return (0)
@0x04492802:[T:0x411b9b60] CE - Engine_fwriteTrace> got 149 chars
@0x44924d1 (0 still avail, max: 32744, lost: 0)
@0x044ddf00:[T:0x411b9b60] CE - Engine_fwriteTrace(0x268c8, '', 0x26458)
@0x044ddfc9:[T:0x411b9b60] CE - Engine_fwriteTrace(): requesting DSP
trace @0x44ddfba ...
@0x044de04c:[T:0x411b9b60] OC - Comm_put> Enter(msgqQueue=0x0, msg=0x4094b800)
@0x044de0f4:[T:0x411b9b60] OC - Comm_put> return (0)
@0x044de1bb:[T:0x411b9b60] OC - Comm_get> Enter(msgqQueue=0x10001,
msg=0x411b9590, timeout=-1)
@0x044de260:[T:0x411b9b60] OC - Comm_get> return (0)
@0x044de2de:[T:0x411b9b60] CE - Engine_fwriteTrace> got 149 chars
@0x44ddfba (0 still avail, max: 32744, lost: 0)
#end of file
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