You're both looking at documents that do not apply to the DM6446. Please go to the DM6446 product folder for documents applicable to this device:
http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html#technicald ocuments Kashin, the guide you are looking at applies to 64x cache, not 64x+ cache. The correct guide, as seen in the product folder above, is: http://focus.ti.com/dsp/docs/dspsupporttechdocsc.tsp?sectionId=3&tabId=4 09&familyId=1302&abstractName=spru862a Andre, there is not a CSL for DM6446 and so those CSL commands should not be used (they are written for 64x, not 64x+). DSP/BIOS has a set of APIs, BCACHE, that can be used for modifying the cache settings at run-time. These APIs are described in the BIOS documentation. You can find the BIOS documentation inside the individual BIOS releases. For example: bios_5_32_02/packages/ti/bios/doc To answer the original questions: 1) A new feature of the 64x+ cache is that L1 memory is also configurable as either SRAM or cache. The hardware defaults to 32KB L1P and 32KB L1D. However, your BIOS tcf file can override this. 2) The L2 defaults to all SRAM. However, this also can be overridden in the BIOS tcf file. When data buffers are stored in L1D or L2 you do not need to worry at all about cache coherence as that will be handled by the hardware. However, if your data is stored in external memory, then you must be more careful with coherence if the data is being accessed by more than one source (e.g. ARM, DSP, EDMA, etc.). Turning on the L2 cache is not enough for external memory to actually get cached. There are a set of registers called MAR (memory attribute register) where you must set the bit corresponding to a range of DDR in order for that range to be cacheable. Brad > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf > Of Andre Gaschler > Sent: Wednesday, June 11, 2008 4:20 AM > To: kashin Lin > Cc: davinci-linux-open-source@linux.davincidsp.com > Subject: Re: About the cache issues of dm6446 > > > Hi, > > for enabling caches in run time have a look into > http://focus.ti.com/lit/ug/spru401j/spru401j.pdf > especially the CACHE section. > > If you want access CMEM/DSPLINK data for example (that should be in DDR > 0x87 - 0x88 ) you simply #include <csl_cache.h> to your DSP code and write > CACHE_enableCaching ( CACHE_EMIFA_CE07 ) ; // Cache CMEM/DSPLINK area > that is at the end of DDR memory > > L2SRAM is cached by default, DDR is not (so you probably want to enable > that in run time). > > -- Andre > > > > > > > > ------------------------------------------------------------------------ > > > > Subject: > > About the cache issues of dm6446 > > From: > > "kashin Lin" <[EMAIL PROTECTED]> > > Date: > > Wed, 11 Jun 2008 15:51:23 +0800 > > To: > > davinci-linux-open-source@linux.davincidsp.com > > > > To: > > davinci-linux-open-source@linux.davincidsp.com > > > > > > Hi, > > > > i have read the "DSP two-level internal memory reference guide > > (spru610)" & "DSP cache user guide (spru656)" but > > still have some questions about the dm6446 DSP side's cache: > > > > 1. by reading these two guides, it seems that level-1 memory ( L1D, > > L1P) are always used as cache and level-2 can be configured as > > SRAM or cache. but i found that on the dm6446 memory map described > > in sprs283 and .tcf file when using DSP/BIOS, there > > is a memory region named L1D RAM ranged from 0x11f04000 ~ > > 0x11f0ffff and another named L1D RAM/cache ranged from > > 0x11f10000 ~ 0x11f17fff. does it mean L1D can also be configured as > > RAM or cache? how? any restriction? > > > > 2. when using DSP/BIOS on dm6446, does it defaultly set all L2 memory > > as SRAM (64K) and L1D and L1P as caches? should i enable the caches > > in run-time? and what are the default cacheability setting of > > L2SRAM and DDR(external memory)? > > > > thanks in advance. > > > > best, > > kashin lin > > ------------------------------------------------------------------------ > > > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source@linux.davincidsp.com > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source@linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
