Hey all,
I'm using the DM355 chip mated with an FPGA that produces an
I2S compliant bit stream - I did not have to modify the davinci audio
drivers since the FPGA produces an exact bitstream as the TLV320AIC33
chip does (16 bit samples, L and R on a I2S line); On the application
side, I'm using the encode demo to do both video and audio capture to
files.
I'm noticing a few things on the encode demo application - the FPGA can
be setup to produce a test stream (the I2S 16 bit samples increase by 1,
like a counter so that we test for dropped samples on the DM355); When
using the test stream, I find that if I don't do video encoding, the
bitstream received by the DaVinci is 'perfect' - there are no
repeats/drops in the increasing count values.
When I enable video encoding, I start getting random single sample drops
in the received bitstream, i.e the counter values occasionally increase
by 2
I'm using the stock encode demo application.
Initial hunch seems to tell me that it could be a EDMA problem, due to
bus overloading. However, it is always 1-2 samples. It doesn't make
sense that it could be a timing problem - a constant, periodic 1-2
sample drop could not be caused by bus delays since video and audio both
have independent bitrates and are asynchronous, leading to complex
memory access patterns.
I don't think others have noticed this problem on the 355/6446 since
there was no way to conclusively detect single sample drops from the ADC
(it doesn't have a test mode) and you can only notice this when using an
FPGA that can generate custom test patterns. However, this could
manifest on the DVEVM boards as channel swaps
Anyone have any clue?
Thanks a bunch!
Jerry
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