From: David Brownell <[EMAIL PROTECTED]>
Generalize the psc_mux() stuff to stop assuming there are only
DM6446 chips, and specifically to handle things the DM355 EVM
will need: SPI0, MMC0, MMC1, ASP1.
Note that I think the clock framework (PSC) and pinmux framework
really ought to be properly separated. The pinmux stuff seems
like it should fit well into devices-dmXXX.c logic, with boards
declaring what device they use and how they're configured. That
works cleanly on other platforms.
Likewise with muxing IRQ and EDMA channels. Do it all as part
of device setup. (And maybe let it be reconfigured at runtime
for oddball systems.)
Signed-off-by: David Brownell <[EMAIL PROTECTED]>
---
arch/arm/mach-davinci/psc.c | 80 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 1 deletion(-)
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,6 +23,7 @@
#include <linux/init.h>
#include <linux/io.h>
+#include <mach/cpu.h>
#include <mach/hardware.h>
#include <mach/psc.h>
#include <mach/mux.h>
@@ -41,7 +42,9 @@
/* System control register offsets */
#define VDD3P3V_PWDN 0x48
-static void davinci_psc_mux(unsigned int id)
+static void (*davinci_psc_mux)(unsigned int id);
+
+static void dm6446_psc_mux(unsigned int id)
{
switch (id) {
case DAVINCI_LPSC_ATA:
@@ -67,6 +70,72 @@ static void davinci_psc_mux(unsigned int
}
}
+#define DM355_ARM_PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
+#define DM355_ARM_PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10)
+#define DM355_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18)
+#define DM355_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1c)
+
+static void dm355_psc_mux(unsigned int id)
+{
+ u32 tmp;
+
+ /* REVISIT mixing pinmux with PSC setup seems pretty dubious,
+ * especially in cases like ASP0 where there are valid partial
+ * functionality use cases ... like half duplex links. Best
+ * probably to do all this as part of platform_device setup,
+ * while declaring what pins/irqs/edmas/... we care about.
+ */
+ switch (id) {
+ case DM355_LPSC_MMC_SD1: /* MMC1 */
+ /* expose DATA[0..3], CMD, CLK */
+ tmp = davinci_readl(DM355_ARM_PINMUX3);
+ tmp &= ~((3 << 14) | (3 << 12) | (3 << 10) | (3 << 8));
+ tmp |= (1 << 14) | (1 << 12) | (1 << 10) | (1 << 8)
+ | BIT(7) | BIT(6);
+ davinci_writel(tmp, DM355_ARM_PINMUX3);
+ break;
+ case DM355_LPSC_McBSP1: /* ASP1 */
+ /* our ASoC code currently doesn't use these IRQs */
+#if 0
+ /* deliver ASP1_XINT and ASP1_RINT */
+ tmp = davinci_readl(DM355_ARM_INTMUX);
+ tmp |= BIT(6) | BIT(5);
+ davinci_writel(tmp, DM355_ARM_INTMUX);
+#endif
+
+ /* support EDMA for ASP1_RX and ASP1_TX */
+ tmp = davinci_readl(DM355_EDMA_EVTMUX);
+ tmp &= ~(BIT(1) | BIT(0));
+ davinci_writel(tmp, DM355_EDMA_EVTMUX);
+ break;
+ case DAVINCI_LPSC_MMC_SD: /* MMC0 */
+ /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
+ tmp = davinci_readl(DM355_ARM_PINMUX4);
+ tmp &= BIT(2);
+ davinci_writel(tmp, DM355_ARM_PINMUX4);
+
+ /* support EMDA for MMC0 RX */
+ tmp = davinci_readl(DM355_EDMA_EVTMUX);
+ tmp &= ~BIT(2);
+ davinci_writel(tmp, DM355_EDMA_EVTMUX);
+ break;
+ case DAVINCI_LPSC_SPI: /* SPI0 */
+ /* expose SPI0_SDI
+ * NOTE: SPIO_SDENA0 and/or SPIO_SDENA1
+ * will need to be set too.
+ */
+ tmp = davinci_readl(DM355_ARM_PINMUX4);
+ tmp &= ~BIT(1);
+ davinci_writel(tmp, DM355_ARM_PINMUX4);
+ break;
+ }
+}
+
+static void nop_psc_mux(unsigned int id)
+{
+ /* nothing */
+}
+
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
{
@@ -127,6 +196,15 @@ void davinci_psc_config(unsigned int dom
void __init davinci_psc_init(void)
{
+ if (cpu_is_davinci_dm644x()) {
+ davinci_psc_mux = dm6446_psc_mux;
+ } else if (cpu_is_davinci_dm355()) {
+ davinci_psc_mux = dm355_psc_mux;
+ } else {
+ pr_err("PSC: no PSC mux hooks for this CPU\n");
+ davinci_psc_mux = nop_psc_mux;
+ }
+
davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
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