"Mark A. Greer" <mgr...@mvista.com> writes:
> From: Mark A. Greer <mgr...@mvista.com>
>
> The Timer64p timer has 8 compare registers that can
> be used to generate interrupts when the timer value
> matches the compare reg's value. They do not disturb
> the timer itself. This can be useful when there is
> only one timer available for both clock events and
> clocksource.
>
[...]
> diff --git a/arch/arm/mach-davinci/include/mach/time.h
> b/arch/arm/mach-davinci/include/mach/time.h
> index 1c971d8..2587018 100644
> --- a/arch/arm/mach-davinci/include/mach/time.h
> +++ b/arch/arm/mach-davinci/include/mach/time.h
> @@ -30,6 +30,16 @@ enum {
>
> #define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
>
> +/* Offsets of the 8 compare registers */
> +#define CMP12_0 0x60
> +#define CMP12_1 0x64
> +#define CMP12_2 0x68
> +#define CMP12_3 0x6c
> +#define CMP12_4 0x70
> +#define CMP12_5 0x74
> +#define CMP12_6 0x78
> +#define CMP12_7 0x7c
> +
Minor nit: these should be in time.c with the other register offsets,
but I will fix before merging.
Kevin
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