Refer to tms320dm6446.pdf /p14 (datasheet of TMS320DM6446) DSP has only
64KB
The DSP Subsystem includes the following features:
· C64x+ DSP CPU
· 32KB L1 Program (L1P)/Cache (up to 32KB)
· 80KB L1 Data (L1D)/Cache (up to 32KB)
· 64KB Unified Mapped RAM/Cache (L2)
· Little endian
Best regards
Ondrej Pindroch
-----Original Message-----
From: bhushan <saraf.bhus...@gmail.com>
To: jaya.krish...@samsung.com
Cc: "davinci-linux-open-source@linux.davincidsp.com"
<davinci-linux-open-source@linux.davincidsp.com>
Date: Thu, 21 May 2009 14:23:18 +0530
Subject: Re: Unable to change cache size in codec engine.
I am referring doc spru871j.pdf. In the section Level 2 memory and
cache it is mentioned that the L2 cache size can be configured for
32KB, 64KB, 128KB and 256KB. I presume the L2_CACHE is same as this.
If there is any other doc whcih specifies that the cache size
configured is limited to 64KB please refer the same to me.
regards,
Bhushan
On Thu, May 21, 2009 at 1:30 PM, Jaya krishnan
<jaya.krish...@samsung.com> wrote:
> Hello,
> I remember 64x+ L2 cache size is 64K (maximum).
> Regards
> Jayakrishnan
>
>
>
>
> ------- Original Message -------
> Sender : bhushan<saraf.bhus...@gmail.com>
> Date : May 21, 2009 16:19 (GMT+09:00)
> Title : Unable to change cache size in codec engine.
>
> Hello ,
> I am trying to build an application to encode video in mpeg4 format
> and also integrate the scale example from the codec engine in the
> encode combo server. During the integration fro performance reasons I
> want to increase the L2 cache size from 64k to 128k. My processor is
> tms320dm6446.
> On building the codec_server I get the error:
> Error: Can't set cache to size: 128k
> Following is the encode.tcf file:
> /*
> * Setup platform-specific memory map, CLK rate, etc.
> */
> var mem_ext = [
> {
> comment: "DDRALGHEAP: memory for dynamic algmem allocation",
> name: "DDRALGHEAP",
> base: 0x8B800000,
> len: 0x04200000,// 66MB
> space: "code/data"
> },
> {
> comment: "L1DSRAM: memory for dynamic algmem allocation",
> name: "L1DSRAM",
> base: 0x11F04000, //
> len: 0x10000, // 64k
> space: "data"
> },
> {
> comment: "CACHE_L2",
> name: "CACHE_L2",
> base: 0x11800000, //
> len: 0x200000, // 128k
> space: "data"
> },
> {
> comment: "H264ENCSEC1",
> name: "H264ENCSEC1",
> base: 0x8FA00000,
> len: 0x00004140,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC2",
> name: "H264ENCSEC2",
> base: 0x8FA04140,
> len: 0x00005080,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC3",
> name: "H264ENCSEC3",
> base: 0x8FA09220,
> len: 0x00006000,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC4",
> name: "H264ENCSEC4",
> base: 0x8FA10000,
> len: 0x00005000,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC5",
> name: "H264ENCSEC5",
> base: 0x8FA15000,
> len: 0x00003000,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC6",
> name: "H264ENCSEC6",
> base: 0x8FA18000,
> len: 0x00004040,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC7",
> name: "H264ENCSEC7",
> base: 0x8FA28000,
> len: 0x00005400,
> space: "code/data"
> },
> {
> comment: "H264ENCSEC8",
> name: "H264ENCSEC8",
> base: 0x8FA2D400,
> len: 0x00002c00,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC1",
> name: "MPEG4ENCSEC1",
> base: 0x8FA40000,
> len: 0x00010000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC2",
> name: "MPEG4ENCSEC2",
> base: 0x8FA50000,
> len: 0x00008000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC3",
> name: "MPEG4ENCSEC3",
> base: 0x8FA58000,
> len: 0x00008000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC4",
> name: "MPEG4ENCSEC4",
> base: 0x8FA60000,
> len: 0x00008000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC5",
> name: "MPEG4ENCSEC5",
> base: 0x8FA68000,
> len: 0x00008000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC6",
> name: "MPEG4ENCSEC6",
> base: 0x8FA70000,
> len: 0x00008000,
> space: "code/data"
> },
> {
> comment: "MPEG4ENCSEC7",
> name: "MPEG4ENCSEC7",
> base: 0x8FA78000,
> len: 0x00010000,
> space: "code/data"
> },
>
> {
>
> comment: "DDR: memory for code and data",
> name: "DDR",
> base: 0x8FB00000,
> len: 0x00300000,
> space: "code/data"
> },
>
>
> {
> comment: "DSPLINK: memory for DSPLINK code and data",
> name: "DSPLINKMEM",
> base: 0x8FE00000, // 254MB
> len: 0x00100000, // 1MB
> space: "code/data"
> },
> {
> comment: "RESET_VECTOR: memory for the reset vector table",
> name: "RESET_VECTOR",
> base: 0x8FF00000,
> len: 0x00000080,
> space: "code/data"
> },
> ];
>
> /* Specify the L2 memory setting */
> var device_regs = {
> l2Mode: "128k"
> };
>
> var params = {
> clockRate: 594,
> catalogName: "ti.catalog.c6000",
> deviceName: "DM6446",
> regs: device_regs,
> mem: mem_ext
> };
>
> /*
> * Customize generic platform with parameters specified above.
> */
> utils.loadPlatform("ti.platforms.generic", params);
>
> /*
===========================================================================
> * Enable heaps and tasks
> *
===========================================================================
> */
> bios.enableMemoryHeaps(prog);
> bios.enableTskManager(prog);
>
> /*
===========================================================================
> * Create heaps in memory segments that are to have heap
> *
===========================================================================
> */
> bios.DDR.createHeap = true;
> bios.DDR.heapSize = 0x10000; // 256K
>
> bios.DDRALGHEAP.createHeap = true;
> bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len;
>
> /*
> * Enable heaps in the L1DSRAM (internal L1 cache ram, fixed size)
> * and define the label for heap usage.
> */
> bios.L1DSRAM.createHeap = true;
> bios.L1DSRAM.enableHeapLabel = true;
> bios.L1DSRAM.len = 0x10000;
> bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP");
> bios.L1DSRAM.heapSize = 0x10000;
>
> /*
===========================================================================
> * GBL
> *
===========================================================================
> */
> prog.module("GBL").ENABLEALLTRC = false;
> prog.module("GBL").PROCID = 0;
> prog.module("GBL").CALLUSERINITFXN = 1;
> /* user init function calls Link's HAL initialization */
> prog.module("GBL").USERINITFXN = prog.extern("HAL_init");
>
> prog.module("GBL").C64PLUSCONFIGURE = true ;
> prog.module("GBL").C64PLUSL2CFG = "128k" ;
> prog.module("GBL").C64PLUSL1DCFG = "16k" ;
> prog.module("GBL").C64PLUSL1PCFG = "32k" ;
> prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;
>
> /* CPU load computation */
> var cpuLoad = prog.module("IDL").create("Global_cpuLoad");
>
> cpuLoad.fxn = prog.extern("LOAD_idlefxn");
>
> cpuLoad.calibration = true;
>
>
>
> /*
===========================================================================
> * HWI
> *
===========================================================================
> */
> bios.HWI_INT4.interruptSelectNumber = 16
> bios.HWI_INT5.interruptSelectNumber = 17
>
> /*
===========================================================================
> * MEM
> *
===========================================================================
> */
> prog.module("MEM").STACKSIZE = 0x1000 ;
>
> /*
===========================================================================
> * Global Settings
> *
===========================================================================
> */
> prog.module("MEM").ARGSSIZE = 200;
>
> /*
===========================================================================
> * Enable MSGQ and POOL Managers
> *
===========================================================================
> */
> bios.MSGQ.ENABLEMSGQ = true;
> bios.POOL.ENABLEPOOL = true;
>
> /*
===========================================================================
> * Set all code and data sections to use DDR
> *
===========================================================================
> */
> bios.setMemCodeSections (prog, bios.DDR) ;
> bios.setMemDataNoHeapSections (prog, bios.DDR) ;
> bios.setMemDataHeapSections (prog, bios.DDRALGHEAP) ;
>
> /*
===========================================================================
> * MEM : IRAM
> *
===========================================================================
> */
> //var IRAM = prog.module("MEM").instance("IRAM");
> //IRAM.len = 0x800;
>
> /*
===========================================================================
> * MEM : Global
> *
===========================================================================
> */
> prog.module("MEM").BIOSOBJSEG = bios.DDRALGHEAP;
> prog.module("MEM").MALLOCSEG = bios.DDRALGHEAP;
>
> /*
===========================================================================
> * TSK : Global
> *
===========================================================================
> */
> prog.module("TSK").STACKSEG = bios.DDRALGHEAP ;
>
> /*
===========================================================================
> * Generate configuration files...
> *
===========================================================================
> */
> if (config.hasReportedError == false) {
> prog.gen();
> }
>
> If anyone has any suggestion or information on how to go about
> changing the cache size in this file or using bios apis please reply,
> Thanks in advance
> --
> Bhushan
>
> _______________________________________________
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>
--
Bhushan
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