Hi, For my 480x272 TFT LCD I want to generate a 9Mhz VCLK using PLL2 mode (sprue14b 5.2.5). In order to do that I want to set
-PLLM of PLL2 to "x10" -PLLDIV1 to "/15" -PLLDIV2 to "/1" -VENC_DIV_2 to "/2" so that I can modify 27MHz MXI to x10 /15 /2 = 9 MHz. and I also want to set the timing signals for proper sync. signals in logicpd_encoder.c. but I could not find in which portion of the code these PLL registers are initialized. Could you please help me to change these registers? Is there any documents, application reports and patches which help me to modify the VPBE driver for different resolution LCDs? Ferhat
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