Nori, Sekhar <nsek...@ti.com> writes:
> The patch allows Async3 clock source to be selected between PLL1 SYSCLK2
> and PLL0 SYSCLK2.
>
> Having Async3 source from PLL1 SYSCLK2 allows peripherals on that
> domain to remain unaffected by frequency scaling on PLL0.
>
> Signed-off-by: Sekhar Nori <nsek...@ti.com>
>
> ---
> arch/arm/mach-davinci/clock.h | 4 +-
> arch/arm/mach-davinci/da850.c | 39
> ++++++++++++++++++++++++++++
> arch/arm/mach-davinci/include/mach/da8xx.h | 1 +
> 3 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
> index 74e0389..0b06121 100644
> --- a/arch/arm/mach-davinci/clock.h
> +++ b/arch/arm/mach-davinci/clock.h
> @@ -69,9 +69,9 @@ struct clk {
> const char *name;
> unsigned long rate;
> u8 usecount;
> - u8 flags;
> u8 lpsc;
> u8 psc_ctlr;
> + u32 flags;
> struct clk *parent;
> struct pll_data *pll_data;
> u32 div_reg;
> @@ -79,7 +79,7 @@ struct clk {
> int (*round_rate) (struct clk *clk, unsigned long rate);
> };
>
> -/* Clock flags */
> +/* Clock flags: SoC-specific flags start at BIT(16) */
> #define ALWAYS_ENABLED BIT(1)
> #define CLK_PSC BIT(2)
> #define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index 192d719..4123ea5 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -30,12 +30,17 @@
> #include "clock.h"
> #include "mux.h"
>
> +/* SoC specific clock flags */
> +#define DA850_CLK_ASYNC3 BIT(16)
> +
> #define DA850_PLL1_BASE 0x01e1a000
> #define DA850_TIMER64P2_BASE 0x01f0c000
> #define DA850_TIMER64P3_BASE 0x01f0d000
>
> #define DA850_REF_FREQ 24000000
>
> +#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
> +
> static struct pll_data pll0_data = {
> .num = 1,
> .phys_base = DA8XX_PLL0_BASE,
> @@ -232,6 +237,7 @@ static struct clk uart1_clk = {
> .name = "uart1",
> .parent = &pll0_sysclk2,
> .lpsc = DA8XX_LPSC1_UART1,
> + .flags = DA850_CLK_ASYNC3,
> .psc_ctlr = 1,
> };
>
> @@ -239,6 +245,7 @@ static struct clk uart2_clk = {
> .name = "uart2",
> .parent = &pll0_sysclk2,
> .lpsc = DA8XX_LPSC1_UART2,
> + .flags = DA850_CLK_ASYNC3,
> .psc_ctlr = 1,
> };
>
> @@ -790,6 +797,36 @@ static struct davinci_timer_info da850_timer_info = {
> .clocksource_id = T0_TOP,
> };
>
> +#ifdef CONFIG_CPU_FREQ
How about leave this without an #ifdef, and make da850_init() have
the #ifdef so it is always called on boot.
BTW, is there a reason to not have the CPUfreq settings be the
default?
> +static void da850_set_async3_src(int pllnum)
> +{
> + struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
> + struct davinci_clk *c;
> + unsigned int v;
> + int ret;
> +
> + for (c = da850_clks; c->lk.clk; c++) {
> + clk = c->lk.clk;
> + if (clk->flags & DA850_CLK_ASYNC3) {
> + ret = clk_set_parent(clk, newparent);
> + WARN(ret, "DA850: unable to re-parent clock %s",
> + clk->name);
> + }
> + }
> +
> + v = __raw_readl(IO_ADDRESS(DA8XX_CFGCHIP3_REG));
> + if (pllnum)
> + v |= CFGCHIP3_ASYNC3_CLKSRC;
> + else
> + v &= ~CFGCHIP3_ASYNC3_CLKSRC;
> + __raw_writel(v, IO_ADDRESS(DA8XX_CFGCHIP3_REG));
We're moving to getting rid of IO_ADDRESS() macro.
Instead, define the *_REG values as offsets from the base, ioremap()
the base address and then use read*/write* to access using 'base +
offset' values. You'll probably want to ioremap() in init instead of
each time, but you can make that call.
> +}
> +#else
> +static void da850_set_async3_src(int pllnum)
> +{
> +}
> +#endif
> +
> static struct davinci_soc_info davinci_soc_info_da850 = {
> .io_desc = da850_io_desc,
> .io_desc_num = ARRAY_SIZE(da850_io_desc),
> @@ -817,4 +854,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
> void __init da850_init(void)
> {
> davinci_common_init(&davinci_soc_info_da850);
> +
> + da850_set_async3_src(1);
> }
> diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h
> b/arch/arm/mach-davinci/include/mach/da8xx.h
> index d4095d0..e3eb953 100644
> --- a/arch/arm/mach-davinci/include/mach/da8xx.h
> +++ b/arch/arm/mach-davinci/include/mach/da8xx.h
> @@ -30,6 +30,7 @@
> #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
>
> #define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000)
> +#define DA8XX_CFGCHIP3_REG (DA8XX_BOOT_CFG_BASE + 0x188)
>
> #define DA8XX_PSC0_BASE 0x01c10000
> #define DA8XX_PLL0_BASE 0x01c11000
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