This might help clear things up, from the ARM10 product announcement visible at http://bwrc.eecs.berkeley.edu/CIC/announce/1998/arm10.annc.html
---------- The ARM10TDMI processor core is the first implementation of the ARMv5T Instruction Set Architecture (ISA). ARMv5T is a superset of the ARMv4 ISA implemented by the StrongARM processors and the ARMv4T ISA implemented by the ARM7 Thumb Family and ARM9 Thumb Family processors. The ARM10TDMI core employs parallel instruction execution, branch prediction, and the ability to continue executing in the presence of a cache miss to achieve high performance on real applications. ---------- M -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
