--- Begin Message ---
Source: leveldb
Version: 0+20110901.git7263023-2
Severity: serious
Justification: fails to build from source
Tags: patch
Hi,
leveldb FTBFS some architecture.
https://buildd.debian.org/status/package.php?p=leveldb&suite=sid
http://buildd.debian-ports.org/status/package.php?p=leveldb&suite=sid
Because leveldb does not support these architecture.
-----
dh_auto_configure -O--parallel
dh_auto_build -O--parallel
make[1]: Entering directory
`/build/buildd-leveldb_0+20110901.git7263023-2-ia64-gm7mku/leveldb-0+20110901.git7263023'
g++ -g -O2 -c -I. -I./include -fno-builtin-memcmp
-DLEVELDB_PLATFORM_POSIX -pthread -DOS_LINUX -O2 -DNDEBUG
-fPIC db/builder.cc -o db/builder.o
g++ -g -O2 -c -I. -I./include -fno-builtin-memcmp
-DLEVELDB_PLATFORM_POSIX -pthread -DOS_LINUX -O2 -DNDEBUG
-fPIC db/c.cc -o db/c.o
In file included from ./port/port_posix.h:28:0,
from ./port/port.h:14,
from ./db/filename.h:14,
from db/builder.cc:7:
./port/atomic_pointer.h:133:2: error: #error Please implement
AtomicPointer for this platform.
make[1]: *** [db/builder.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory
`/build/buildd-leveldb_0+20110901.git7263023-2-ia64-gm7mku/leveldb-0+20110901.git7263023'
dh_auto_build: make -j2 returned exit code 2
make: *** [build] Error 2
-----
I created patch which revise this problem.
Could you check and apply these?
I tested on i386, amd64 and sh4.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
From 9257ab3a17963b043dbc6e53a094e13a5b54488c Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:25:23 +0900
Subject: [PATCH 1/9] Add ReadMemoryBarrier and WriteMemoryBarrier methods
Some CPUs differ in the order of the memory barrier of read and write.
For other CPUs, this adds the memory barrier method the memory barrier
for read and write metohds.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 31 +++++++++++++++++++++++++------
1 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index c20b1bd..022a3a6 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -48,9 +48,17 @@ namespace port {
// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
#define LEVELDB_HAVE_MEMORY_BARRIER
+#define ReadMemoryBarrier MemoryBarrier()
+#define WriteMemoryBarrier MemoryBarrier()
+
// Gcc on x86
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
__asm__ __volatile__("" : : : "memory");
@@ -59,7 +67,12 @@ inline void MemoryBarrier() {
// Sun Studio
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ asm volatile("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
asm volatile("" : : : "memory");
@@ -68,7 +81,10 @@ inline void MemoryBarrier() {
// Mac OS
#elif defined(OS_MACOSX)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ OSMemoryBarrier();
+}
+inline void WriteMemoryBarrier() {
OSMemoryBarrier();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
@@ -78,7 +94,10 @@ inline void MemoryBarrier() {
typedef void (*LinuxKernelMemoryBarrierFunc)(void);
LinuxKernelMemoryBarrierFunc pLinuxKernelMemoryBarrier __attribute__((weak)) =
(LinuxKernelMemoryBarrierFunc) 0xffff0fa0;
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ pLinuxKernelMemoryBarrier();
+}
+inline void WriteMemoryBarrier() {
pLinuxKernelMemoryBarrier();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
@@ -97,11 +116,11 @@ class AtomicPointer {
inline void NoBarrier_Store(void* v) { rep_ = v; }
inline void* Acquire_Load() const {
void* result = rep_;
- MemoryBarrier();
+ ReadMemoryBarrier();
return result;
}
inline void Release_Store(void* v) {
- MemoryBarrier();
+ WriteMemoryBarrier();
rep_ = v;
}
};
--
1.7.6.3
From 6805877f8913935071fb97c1b76e4f0ce992d8a6 Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:27:19 +0900
Subject: [PATCH 2/9] Add support PPC
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 022a3a6..0111c8c 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -36,6 +36,8 @@
#define ARCH_CPU_X86_FAMILY 1
#elif defined(__ARMEL__)
#define ARCH_CPU_ARM_FAMILY 1
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__)
+#define ARCH_CPU_PPC_FAMILY 1
#endif
namespace leveldb {
@@ -102,6 +104,21 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// PPC
+#elif defined(ARCH_CPU_PPC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+#ifdef __powerpc64__
+ __asm__ __volatile__ ("lwsync" : : : "memory");
+#else
+ __asm__ __volatile__ ("sync" : : : "memory");
+#endif
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -156,6 +173,7 @@ class AtomicPointer {
#undef LEVELDB_HAVE_MEMORY_BARRIER
#undef ARCH_CPU_X86_FAMILY
#undef ARCH_CPU_ARM_FAMILY
+#undef ARCH_CPU_PPC_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From 3d7e949eea9dc740adda58a29d5f688d50a66c2c Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:27:58 +0900
Subject: [PATCH 3/9] Add support IA64
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 0111c8c..f1aac8c 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -38,6 +38,8 @@
#define ARCH_CPU_ARM_FAMILY 1
#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__)
#define ARCH_CPU_PPC_FAMILY 1
+#elif defined(__ia64__)
+#define ARCH_CPU_IA64_FAMILY 1
#endif
namespace leveldb {
@@ -119,6 +121,16 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// IA64
+#elif defined(ARCH_CPU_IA64_FAMILY)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -174,6 +186,7 @@ class AtomicPointer {
#undef ARCH_CPU_X86_FAMILY
#undef ARCH_CPU_ARM_FAMILY
#undef ARCH_CPU_PPC_FAMILY
+#undef ARCH_CPU_IA64_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From bd476d4802203af1f788bf428b26ca429afe61c2 Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:28:40 +0900
Subject: [PATCH 4/9] Add support Alpha
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index f1aac8c..6d0b15f 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -40,6 +40,8 @@
#define ARCH_CPU_PPC_FAMILY 1
#elif defined(__ia64__)
#define ARCH_CPU_IA64_FAMILY 1
+#elif defined(__alpha__)
+#define ARCH_CPU_ALPHA_FAMILY 1
#endif
namespace leveldb {
@@ -131,6 +133,17 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// ALPHA
+#elif defined(ARCH_CPU_ALPHA_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("mb" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("wmb" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -187,6 +200,7 @@ class AtomicPointer {
#undef ARCH_CPU_ARM_FAMILY
#undef ARCH_CPU_PPC_FAMILY
#undef ARCH_CPU_IA64_FAMILY
+#undef ARCH_CPU_ALPHA_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From bc03fac68e487d0aa367b93794177178a1f9f1ab Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:29:28 +0900
Subject: [PATCH 5/9] Add support S390
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 6d0b15f..03a1815 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -42,6 +42,8 @@
#define ARCH_CPU_IA64_FAMILY 1
#elif defined(__alpha__)
#define ARCH_CPU_ALPHA_FAMILY 1
+#elif defined(__s390x__) || defined(__s390__)
+#define ARCH_CPU_S390_FAMILY 1
#endif
namespace leveldb {
@@ -144,6 +146,17 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// S390
+#elif defined(ARCH_CPU_S390_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ volatile("bcr 15,0" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ volatile("bcr 15,0" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -201,6 +214,7 @@ class AtomicPointer {
#undef ARCH_CPU_PPC_FAMILY
#undef ARCH_CPU_IA64_FAMILY
#undef ARCH_CPU_ALPHA_FAMILY
+#undef ARCH_CPU_S390_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From 598ee273a96c76d4199171d529a99e12c738d847 Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:30:07 +0900
Subject: [PATCH 6/9] Add support Sparc
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 03a1815..aae1761 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -44,6 +44,8 @@
#define ARCH_CPU_ALPHA_FAMILY 1
#elif defined(__s390x__) || defined(__s390__)
#define ARCH_CPU_S390_FAMILY 1
+#elif defined(__sparc__) || defined(__sparc64__)
+#define ARCH_CPU_SPARC_FAMILY 1
#endif
namespace leveldb {
@@ -157,6 +159,17 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// SPARC
+#elif defined(ARCH_CPU_SPARC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -215,6 +228,7 @@ class AtomicPointer {
#undef ARCH_CPU_IA64_FAMILY
#undef ARCH_CPU_ALPHA_FAMILY
#undef ARCH_CPU_S390_FAMILY
+#undef ARCH_CPU_SPARC_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From db2149d44c5664cdfdbc71e9f793c672017481c7 Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:30:41 +0900
Subject: [PATCH 7/9] Add support MIPS
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index aae1761..4c3d2d6 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -46,6 +46,8 @@
#define ARCH_CPU_S390_FAMILY 1
#elif defined(__sparc__) || defined(__sparc64__)
#define ARCH_CPU_SPARC_FAMILY 1
+#elif defined(__mips__) || defined(__mips64__)
+#define ARCH_CPU_MIPS_FAMILY 1
#endif
namespace leveldb {
@@ -170,6 +172,17 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// MIPS
+#elif defined(ARCH_CPU_MIPS_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -229,6 +242,7 @@ class AtomicPointer {
#undef ARCH_CPU_ALPHA_FAMILY
#undef ARCH_CPU_S390_FAMILY
#undef ARCH_CPU_SPARC_FAMILY
+#undef ARCH_CPU_MIPS_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From 10d362d14e201136a6a47e98c3b6433b36b8fe8d Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:31:09 +0900
Subject: [PATCH 8/9] Add support SuperH
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 4c3d2d6..9bf3b14 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -48,6 +48,8 @@
#define ARCH_CPU_SPARC_FAMILY 1
#elif defined(__mips__) || defined(__mips64__)
#define ARCH_CPU_MIPS_FAMILY 1
+#elif defined(__sh__)
+#define ARCH_CPU_SH_FAMILY 1
#endif
namespace leveldb {
@@ -183,6 +185,25 @@ inline void WriteMemoryBarrier() {
}
#define LEVELDB_HAVE_MEMORY_BARRIER
+// SH
+#elif defined(ARCH_CPU_SH_FAMILY)
+#if defined(__SH4A__) || defined(__SH5__)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+#else
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+#endif
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -243,6 +264,7 @@ class AtomicPointer {
#undef ARCH_CPU_S390_FAMILY
#undef ARCH_CPU_SPARC_FAMILY
#undef ARCH_CPU_MIPS_FAMILY
+#undef ARCH_CPU_SH_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
From f9416ddac7ddc73b2998764d6db85297b831602a Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <[email protected]>
Date: Wed, 28 Sep 2011 12:36:41 +0900
Subject: [PATCH 9/9] Add support PARISC
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
port/atomic_pointer.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
index 9bf3b14..348d02c 100644
--- a/port/atomic_pointer.h
+++ b/port/atomic_pointer.h
@@ -50,6 +50,8 @@
#define ARCH_CPU_MIPS_FAMILY 1
#elif defined(__sh__)
#define ARCH_CPU_SH_FAMILY 1
+#elif defined(__hppa__) || defined(__parisc__)
+#define ARCH_CPU_PARISC_FAMILY 1
#endif
namespace leveldb {
@@ -204,6 +206,17 @@ inline void WriteMemoryBarrier() {
#endif
#define LEVELDB_HAVE_MEMORY_BARRIER
+// PARISC
+#elif defined(ARCH_CPU_PARISC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
#endif
// AtomicPointer built using platform-specific MemoryBarrier()
@@ -265,6 +278,7 @@ class AtomicPointer {
#undef ARCH_CPU_SPARC_FAMILY
#undef ARCH_CPU_MIPS_FAMILY
#undef ARCH_CPU_SH_FAMILY
+#undef ARCH_CPU_PARISC_FAMILY
} // namespace leveldb::port
} // namespace leveldb
--
1.7.6.3
--- End Message ---
