Source: valgrind
Version: 1:3.10.1-3
Severity: important
Tags: upstream patch
Forwarded: https://bugs.kde.org/show_bug.cgi?id=348924

Hi,

For mips and mipsel, the plan is to enable the FPXX ABI when GCC 5 is
made the default compiler.

See these for more information:
https://bugs.debian.org/789612
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Packages which only use C will compile file and most MIPS assembly will
work except for code which uses the odd numbered FPU registers which
are now unavailable for direct access.

valgrind is one of the few packages which does this, so I needed to
apply the attached patch to get it to compile with fpxx enabled (sorry
the patch is applied to VEX so you will need to add 'a/VEX' to the
paths).

Thanks,
James
Index: priv/guest_mips_helpers.c
===================================================================
--- priv/guest_mips_helpers.c	(revision 3151)
+++ priv/guest_mips_helpers.c	(working copy)
@@ -1122,14 +1122,13 @@
 
 #define ASM_VOLATILE_UNARY32_DOUBLE(inst)                           \
    __asm__ volatile("cfc1  $t0,  $31"   "\n\t"                      \
-                    "ctc1  %3,   $31"   "\n\t"                      \
-                    "mtc1  %1,   $f20"  "\n\t"                      \
-                    "mtc1  %2,   $f21"  "\n\t"                      \
+                    "ctc1  %2,   $31"   "\n\t"                      \
+                    "ldc1  $f20, 0(%1)"  "\n\t"                     \
                     #inst" $f20, $f20"  "\n\t"                      \
                     "cfc1  %0,   $31"   "\n\t"                      \
                     "ctc1  $t0,  $31"   "\n\t"                      \
                     : "=r" (ret)                                    \
-                    : "r" (loFsVal), "r" (hiFsVal), "r" (fcsr)      \
+                    : "r" (&fsVal), "r" (fcsr)                      \
                     : "t0", "$f20", "$f21"                          \
                    );
 
@@ -1160,17 +1159,14 @@
 
 #define ASM_VOLATILE_BINARY32_DOUBLE(inst)                          \
    __asm__ volatile("cfc1  $t0,  $31"         "\n\t"                \
-                    "ctc1  %5,   $31"         "\n\t"                \
-                    "mtc1  %1,   $f20"        "\n\t"                \
-                    "mtc1  %2,   $f21"        "\n\t"                \
-                    "mtc1  %3,   $f22"        "\n\t"                \
-                    "mtc1  %4,   $f23"        "\n\t"                \
+                    "ctc1  %3,   $31"         "\n\t"                \
+                    "ldc1  $f20, 0(%1)"  "\n\t"                     \
+                    "ldc1  $f22, 0(%2)"  "\n\t"                     \
                     #inst" $f20, $f20, $f22"  "\n\t"                \
                     "cfc1  %0,   $31"         "\n\t"                \
                     "ctc1  $t0,  $31"         "\n\t"                \
                     : "=r" (ret)                                    \
-                    : "r" (loFsVal), "r" (hiFsVal), "r" (loFtVal),  \
-                      "r" (hiFtVal), "r" (fcsr)                     \
+                    : "r" (&fsVal), "r" (&ftVal), "r" (fcsr)        \
                     : "t0", "$f20", "$f21", "$f22", "$f23"          \
                    );
 
@@ -1209,6 +1205,8 @@
    loFtVal    = (UInt)addr[ft*2];
    hiFtVal    = (UInt)addr[ft*2+2];
 #endif
+   ULong fsVal   = loFsVal | ((ULong) hiFsVal) << 32;
+   ULong ftVal   = loFtVal | ((ULong) hiFtVal) << 32;
    UInt fcsr     = guest_state->guest_FCSR;
    switch (inst) {
       case ROUNDWD:

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