On 04/12/2019 16.15, Brice Goglin wrote: > PCIe links (since Gen3) are encoded 128 data rate over 130 signal rate. > That's why you get 3.93 (truncated to 3.9). We decided to keep that > value exact in hwloc because the data/signal rate is different among > PCIe generations. We could round it up to 4 in the lstopo output, but I > am not sure where to start (PCIe Gen4 16x is 31.5GB/s instead of 32 and > Gen5 will be 63 instead of 64, those are harder to round up).
Thanks for the detailed explanation! How about displaying the PCIe generation and number of links? -- Laurent.
