Package: binutils-common
Version: 2.42-4
Severity: minor
Tags: patch
Dear Maintainer,
here are some notes and editorial fixes for the manual.
The patch is in the attachment.
-.-
The man page is created by Pod::Man. So fixes should be
applied to the source file for the man page, and maybe to the
creating process files (commands).
-,-
The difference between the formatted outputs can be seen with:
nroff -man <file1> > <out1>
nroff -man <file2> > <out2>
diff -u <out1> <out2>
and for groff, using
"printf '%s\n%s\n' '.kern 0' '.ss 12 0' | groff -man -Z - "
instead of "nroff -man"
Add the option "-t", if the file contains a table.
Read the output of "diff -u" with "less -R" or similar.
-.-.
If "man" (man-db) is used to check the manual for warnings,
the following must be set:
The option "-warnings=w"
The environmental variable:
export MAN_KEEP_STDERR=yes (or any non-empty value)
or
(produce only warnings):
export MANROFFOPT="-ww -z"
export MAN_KEEP_STDERR=yes (or any non-empty value)
-.-.
Output from "mandoc -T lint as.1":
N.B. Not in the patch.
mandoc: as.1:578:82: STYLE: input text line longer than 80 bytes: symbols with
the \f(...
mandoc: as.1:596:89: STYLE: input text line longer than 80 bytes: ECOFF or
DWARF2. Wh...
mandoc: as.1:613:81: STYLE: input text line longer than 80 bytes: may help
debugging a...
mandoc: as.1:678:85: STYLE: input text line longer than 80 bytes: Add directory
\fIdir...
mandoc: as.1:752:90: STYLE: input text line longer than 80 bytes: Each input
function ...
mandoc: as.1:753:89: STYLE: input text line longer than 80 bytes: should
ideally be cl...
mandoc: as.1:754:87: STYLE: input text line longer than 80 bytes: each
\f(CW\*(C`.type...
mandoc: as.1:755:84: STYLE: input text line longer than 80 bytes: Descriptor
Entry). ...
mandoc: as.1:823:91: STYLE: input text line longer than 80 bytes: are:
\f(CW\*(C`ilp32...
mandoc: as.1:824:84: STYLE: input text line longer than 80 bytes: file in ELF32
and EL...
mandoc: as.1:869:83: STYLE: input text line longer than 80 bytes: The special
name \f(...
mandoc: as.1:914:83: STYLE: input text line longer than 80 bytes: error
message. This...
mandoc: as.1:936:83: STYLE: input text line longer than 80 bytes: The special
name \f(...
mandoc: as.1:939:87: STYLE: input text line longer than 80 bytes: In order to
support ...
mandoc: as.1:942:83: STYLE: input text line longer than 80 bytes: instructions,
while ...
mandoc: as.1:949:81: STYLE: input text line longer than 80 bytes: Enables or
disables ...
mandoc: as.1:977:81: STYLE: input text line longer than 80 bytes: A local
common symbo...
mandoc: as.1:1109:94: STYLE: input text line longer than 80 bytes: when
assembling. Th...
mandoc: as.1:1162:89: STYLE: input text line longer than 80 bytes: It is
ignored on CK8...
mandoc: as.1:1170:92: STYLE: input text line longer than 80 bytes: Pass through
\f(CW\*...
mandoc: as.1:1186:94: STYLE: input text line longer than 80 bytes:
Enable/disable trans...
mandoc: as.1:1200:94: STYLE: input text line longer than 80 bytes:
Enable/disable trans...
mandoc: as.1:1251:88: STYLE: input text line longer than 80 bytes: These
features are a...
mandoc: as.1:1309:24: STYLE: whitespace at end of input line
mandoc: as.1:1523:87: STYLE: input text line longer than 80 bytes: Note that
these exte...
mandoc: as.1:1525:81: STYLE: input text line longer than 80 bytes: suffixes
permitted o...
mandoc: as.1:1623:89: STYLE: input text line longer than 80 bytes: The
\f(CW\*(C`.att_m...
mandoc: as.1:1632:85: STYLE: input text line longer than 80 bytes: The
\f(CW\*(C`.att_s...
mandoc: as.1:1637:101: STYLE: input text line longer than 80 bytes: The
\f(CW\*(C`.att_s...
mandoc: as.1:1917:90: STYLE: input text line longer than 80 bytes: and all call
instruc...
mandoc: as.1:1936:17: STYLE: whitespace at end of input line
mandoc: as.1:1962:88: STYLE: input text line longer than 80 bytes: implicitly
with the ...
mandoc: as.1:2042:83: STYLE: input text line longer than 80 bytes: instructions
or fewe...
mandoc: as.1:2130:86: STYLE: input text line longer than 80 bytes: equivalent
to puttin...
mandoc: as.1:2454:2: WARNING: empty block: RS
mandoc: as.1:2906:81: STYLE: input text line longer than 80 bytes: literals
referenced ...
mandoc: as.1:2912:82: STYLE: input text line longer than 80 bytes: Indicate to
the asse...
mandoc: as.1:2921:82: STYLE: input text line longer than 80 bytes: that the
assembler w...
mandoc: as.1:2946:88: STYLE: input text line longer than 80 bytes: across a
greater ran...
mandoc: as.1:2988:81: STYLE: input text line longer than 80 bytes: mnemonics
starting w...
mandoc: as.1:2992:88: STYLE: input text line longer than 80 bytes: If this
option is no...
-.-.
Remove space characters at the end of lines.
Use "git apply ... --whitespace=fix" to fix extra space issues, or use
global configuration "core.whitespace".
1309:\&\f(CW\*(C`h8300sx\*(C'\fR and
1936:\&\f(CW\*(C`r2\*(C'\fR.
-.-.
Change (or include a "FIXME" paragraph about) misused SI (metric)
numeric prefixes (or names) to the binary ones, like Ki (kibi), Mi
(mebi), Gi (gibi), or Ti (tebi), if indicated.
If the metric prefixes are correct, add the definitions or an
explanation to avoid misunderstanding.
1571:AVX instructions with 128bit vector length, which is the default.
1573:with 256bit vector length.
1601:EVEX instructions with 128bit vector length, which is the default.
1603:encode LIG EVEX instructions with 256bit and 512bit vector length,
-.-.
Mark a full stop (.) and the exclamation mark (!) with "\&",
if it does not mean an end of a sentence.
This is a preventive action,
the paragraph could be reshaped, e.g., after changes.
When typing, one does not always notice when the line wraps after the
period.
There are too many examples of input lines in manual pages,
that end with an abbreviation point.
This marking is robust, and independent of the position on the line.
It corresponds to "\ " in TeX, and to "@:" in Texinfo.
184: [\fB\-march\fR=\fICPU\fR[+\fIEXTENSION\fR...]] [\fB\-mtune\fR=\fICPU\fR]
941:numbered processor names (e.g. 21064) enable the processor-specific PALcode
942:instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR)
do not.
1526:restriction, i.e. despite these otherwise being "enabling" options, using
1703:This option specifies types of branches to align. \fITYPE\fR is
1775:with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not
1776:instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not
2725:required to materialize symbol addresses. (default)
-.-.
Find a repeated word
! 878 --> then
-.-.
Strings longer than 3/4 of a standard line length (80)
N.B. Not in the patch.
120
[\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
191 [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
192 [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
202 [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
209
[\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
298
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
299
\fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mgekko\fR|
300
\fB\-mbroadway\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|
301
\fB\-me6500\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|
302
\fB\-mpower6\fR|\fB\-mpwr6\fR|\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
303
\fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
307
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
343 [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
348
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
349
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
350
\fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
351
\fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
352
\fB\-Asparcvis2\fR|\fB\-Asparcfmaf\fR|\fB\-Asparcima\fR|\fB\-Asparcvis3\fR
354
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
355
\fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
356
\fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
357
\fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
358 \fB\-xarch=sparcvis2\fR|\fB\-xarch=sparcfmaf\fR|\fB\-xarch=sparcima\fR
359 \fB\-xarch=sparcvis3\fR|\fB\-xarch=sparcvisr\fR|\fB\-xarch=sparc5\fR
362 [\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR]
825 .IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
881 .IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1001 .IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1004 .IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1701 .IP \fB\-malign\-branch=\fR\fITYPE\fR\fB[+\fR\fITYPE\fR\fB...]\fR 4
2963 .IP
\fB\-march=\fR\fICPU\fR\fB[\-\fR\fIEXT\fR\fB...][+\fR\fIEXT\fR\fB...]\fR 4
-.-.
Add a comma (or \&) after "e.g." and "i.e.", or use English words
(man-pages(7).
Abbreviation points should be protected against being interpreted as
an end of sentence, if they are not, and that independent of the
current place on the line.
941:numbered processor names (e.g. 21064) enable the processor-specific PALcode
942:instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR)
do not.
1526:restriction, i.e. despite these otherwise being "enabling" options, using
-.-.
Wrong distance between sentences.
Separate the sentences and subordinate clauses; each begins on a new
line. See man-pages(7) ("Conventions for source file layout") and
"info groff" ("Input Conventions").
The best procedure is to always start a new sentence on a new line,
at least, if you are typing on a computer.
Remember coding: Only one command ("sentence") on each (logical) line.
E-mail: Easier to quote exactly the relevant lines.
Generally: Easier to edit the sentence.
Patches: Less unaffected text.
Search for two adjacent words is easier, when they belong to the same line,
and the same phrase.
The amount of space between sentences in the output can then be
controlled with the ".ss" request.
N.B
The number of lines affected is too large to be in the patch.
941:numbered processor names (e.g. 21064) enable the processor-specific PALcode
942:instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR)
do not.
1526:restriction, i.e. despite these otherwise being "enabling" options, using
1534:This option specifies a processor to optimize for. When used in
1663:lock prefix. This option can only be safely used with single-core,
1703:This option specifies types of branches to align. \fITYPE\fR is
1775:with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not
1776:instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not
1944:16 bits of the \fIexpression\fR. If they are all zeros, then LD would
1945:shorten the LDI32 instruction to a single LDI. In such case
\f(CW\*(C`as\*(C'\fR
1949:Assume that LD would not optimize LDI32 instructions. As a consequence,
1953:Do not warn if a label name matches a register name. Usually assembler
1954:programmers will want this warning to be emitted. C compilers may want
2725:required to materialize symbol addresses. (default)
2920:expense in code size. This optimization is enabled by default. Note
2926:across a greater range of addresses. This option should be used when
call
2946:across a greater range of addresses. This option should be used when
jump targets can
2965:This option specifies the target processor. The assembler will issue
2967:will not execute on the target processor. The following processor names
2976:accept some extension mnemonics. For example,
2978:\&\fIIN F,(C)\fR. The following extensions are currently supported:
2995:Mark all labels with specified prefix as local. But such label can be
2996:marked global explicitly in the code. This option do not change default
3000:Accept colonless labels. All symbols at line begin are treated as labels.
3006:Single precision floating point numbers format. Default: ieee754 (32 bit).
3009:Double precision floating point numbers format. Default: ieee754 (64 bit).
-.-.
Split lines longer than 80 characters into two or more lines.
Appropriate break points are the end of a sentence and a subordinate
clause; after punctuation marks.
N.B. Not in the patch.
as.1: line 101 length 81
[\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR]
[\fB\-x\fR]
as.1: line 120 length 100
[\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
as.1: line 150 length 104
[\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR |
\fB\-\-march=common_v10_v32\fR]
as.1: line 157 length 92
[\fB\-force2bsr\fR] [\fB\-mforce2bsr\fR] [\fB\-no\-force2bsr\fR]
[\fB\-mno\-force2bsr\fR]
as.1: line 158 length 89
[\fB\-jsri2bsr\fR] [\fB\-mjsri2bsr\fR] [\fB\-no\-jsri2bsr\fR ]
[\fB\-mno\-jsri2bsr\fR]
as.1: line 209 length 86
[\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
as.1: line 226 length 82
[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization
level\fR]]
as.1: line 227 length 92
[\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR]
[\fB\-call_shared\fR]
as.1: line 229 length 99
[\fB\-mabi\fR=\fIABI\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR]
[\fB\-mfp32\fR] [\fB\-mgp32\fR]
as.1: line 232 length 86
[\fB\-march\fR=\fICPU\fR] [\fB\-mtune\fR=\fICPU\fR] [\fB\-mips1\fR]
[\fB\-mips2\fR]
as.1: line 233 length 86
[\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR]
[\fB\-mips32r2\fR]
as.1: line 234 length 95
[\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR]
[\fB\-mips64r2\fR]
as.1: line 281 length 84
[\fB\-m[no\-]16\-bit\fR] [\fB\-m[no\-]perf\-ext\fR]
[\fB\-m[no\-]perf2\-ext\fR]
as.1: line 282 length 100
[\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR]
[\fB\-m[no\-]div\fR]
as.1: line 283 length 96
[\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR]
[\fB\-m[no\-]fpu\-dp\-ext\fR]
as.1: line 284 length 86
[\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fIFREG\fR]
[\fB\-mreduced\-regs\fR]
as.1: line 285 length 87
[\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR]
[\fB\-mno\-relax\fR]
as.1: line 298 length 138
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
as.1: line 299 length 129
\fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mgekko\fR|
as.1: line 300 length 128
\fB\-mbroadway\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|
as.1: line 301 length 130
\fB\-me6500\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|
as.1: line 302 length 135
\fB\-mpower6\fR|\fB\-mpwr6\fR|\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
as.1: line 303 length 87
\fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
as.1: line 307 length 100
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
as.1: line 337 length 84
[\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR]
[\fB\-march\fR=\fICPU\fR]
as.1: line 348 length 90
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
as.1: line 349 length 87
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
as.1: line 350 length 88
\fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
as.1: line 351 length 88
\fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
as.1: line 354 length 91
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
as.1: line 355 length 86
\fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
as.1: line 356 length 93
\fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
as.1: line 357 length 82
\fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
as.1: line 370 length 89
[\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR]
[\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR]
as.1: line 578 length 82
symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be
controlled
as.1: line 596 length 89
ECOFF or DWARF2. When the debug format is DWARF then a
\f(CW\*(C`.debug_info\*(C'\fR and
as.1: line 597 length 86
\&\f(CW\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file
doesn't
as.1: line 613 length 81
may help debugging assembler code, if the debugger can handle it.
Note\-\-\-this
as.1: line 678 length 85
Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR
directives.
as.1: line 748 length 91
\&\f(CW\*(C`\-\-scfi=experimental\*(C'\fR is not intended to be used for
compiler-generated
as.1: line 752 length 90
Each input function in assembly must begin with the \f(CW\*(C`.type\*(C'\fR
directive, and
as.1: line 753 length 89
should ideally be closed off using a \f(CW\*(C`.size\*(C'\fR directive. When
using SCFI,
as.1: line 754 length 87
each \f(CW\*(C`.type\*(C'\fR directive prompts GAS to start a new FDE (a.k.a.,
Function
as.1: line 755 length 84
Descriptor Entry). This implies that with each \f(CW\*(C`.type\*(C'\fR
directive, a
as.1: line 823 length 91
are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the
generated object
as.1: line 824 length 84
file in ELF32 and ELF64 format respectively. The default is
\f(CW\*(C`lp64\*(C'\fR.
as.1: line 869 length 83
The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to
accept
as.1: line 887 length 120
\&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR,
\f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR
as.1: line 888 length 121
\&\f(CW\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR,
\f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR,
as.1: line 889 length 117
\&\f(CW\*(C`armv8.9\-a\*(C'\fR, \f(CW\*(C`armv8\-r\*(C'\fR,
\f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR,
as.1: line 890 length 94
\&\f(CW\*(C`armv9.2\-a\*(C'\fR, \f(CW\*(C`armv9.3\-a\*(C'\fR and
\f(CW\*(C`armv9.4\-a\*(C'\fR.
as.1: line 914 length 83
error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR
directive.
as.1: line 936 length 83
The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to
accept
as.1: line 939 length 87
In order to support existing practice in OSF/1 with respect to
\f(CW\*(C`.arch\*(C'\fR,
as.1: line 942 length 83
instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do
not.
as.1: line 949 length 81
Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation
for
as.1: line 967 length 86
\&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS
Linker
as.1: line 977 length 81
A local common symbol larger than \fIsize\fR is placed in
\f(CW\*(C`.bss\*(C'\fR,
as.1: line 1109 length 94
when assembling. The BPF ISA versions supported are \fBv1\fR \fBv2\fR,
\fBv3\fR and \fBv4\fR.
as.1: line 1160 length 100
\&\f(CW\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to
\f(CW\*(C`jmpi\*(C'\fR.
as.1: line 1162 length 89
It is ignored on CK801 and CK802 targets, which do not support the
\f(CW\*(C`jmpi\*(C'\fR
as.1: line 1170 length 92
Pass through \f(CW\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for
\f(CW\*(C`bsr\*(C'\fR
as.1: line 1186 length 94
Enable/disable transformation of \f(CW\*(C`jbsr\*(C'\fR instructions to
\f(CW\*(C`bsr\*(C'\fR.
as.1: line 1200 length 94
Enable/disable transformation of \f(CW\*(C`jsri\*(C'\fR instructions to
\f(CW\*(C`bsr\*(C'\fR.
as.1: line 1251 length 88
These features are also enabled implicitly by using \f(CW\*(C`\-mcpu=\*(C'\fR
to specify
as.1: line 1523 length 87
Note that these extension mnemonics can be prefixed with \f(CW\*(C`no\*(C'\fR
to revoke
as.1: line 1525 length 81
suffixes permitted on \f(CW\*(C`\-march=avx10.<N>\*(C'\fR enforce a vector
length
as.1: line 1623 length 89
The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR
directives will
as.1: line 1632 length 85
The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR
directives will
as.1: line 1637 length 101
The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR
directives will take precedent.
as.1: line 1917 length 90
and all call instructions with \f(CW\*(C`jmp\*(C'\fR and
\f(CW\*(C`callr\*(C'\fR sequences
as.1: line 1962 length 88
implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for
targets that
as.1: line 2042 length 83
instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction
there
as.1: line 2102 length 89
\&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file.
\fB\-no\-mips16\fR
as.1: line 2130 length 86
equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the
assembly
as.1: line 2349 length 82
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap
exception
as.1: line 2803 length 124
\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR,
\f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
as.1: line 2811 length 81
\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that
the
as.1: line 2825 length 82
\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of
data
as.1: line 2842 length 85
\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a
value of
as.1: line 2889 length 85
\&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are
grouped into
as.1: line 2891 length 86
\&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals
referenced
as.1: line 2906 length 81
literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions;
literals
as.1: line 2912 length 82
Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use
absolute
as.1: line 2921 length 82
that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR
that
as.1: line 2946 length 88
across a greater range of addresses. This option should be used when jump
targets can
as.1: line 2977 length 92
\&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR
instructions and
as.1: line 2981 length 81
\&\f(CW\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or
\fISL1\fR),
as.1: line 2982 length 92
\&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers:
\fIIXL\fR, \fIIXH\fR,
as.1: line 2984 length 93
\&\f(CW\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp
n,(II+d),R\fR),
as.1: line 2988 length 81
mnemonics starting with \f(CW\*(C`\-\*(C'\fR revoke the respective
functionality:
as.1: line 2989 length 88
\&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extensions
and adds
as.1: line 2992 length 88
If this option is not specified then \f(CW\*(C`\-march=z80+xyhl+infc\*(C'\fR is
assumed.
as.1: line 3012 length 86
\&\fBgcc\fR\|(1), \fBld\fR\|(1), and the Info entries for \fIbinutils\fR and
\fIld\fR.
-.-.
Do not use more than two space characters between sentences or (better)
only a new line character.
2920:expense in code size. This optimization is enabled by default. Note
2926:across a greater range of addresses. This option should be used when
call
2946:across a greater range of addresses. This option should be used when
jump targets can
-.-.
Remove unnecessary second font change in a row or (better) use a
two-fonts macro.
N.B. Not included in the patch.
102: [\fB\-Z\fR] [\fB@\fR\fIFILE\fR]
112: [\fB\-m\fR\fIcpu\fR]
115: [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
119: [\fB\-mcpu=\fR\fIcpu\fR]
153: [\fB\-march=\fR\fIarch\fR] [\fB\-mcpu=\fR\fIcpu\fR]
221: [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR]
[\fB\-mdsp=\fR\fIcpu\fR]
238: [\fB\-mnan=\fR\fIencoding\fR]
279: [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR]
[\fB\-mcpu=\fR\fIcpu\fR]
280: [\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR]
284: [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fIFREG\fR]
[\fB\-mreduced\-regs\fR]
290: [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
291: [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
302:
\fB\-mpower6\fR|\fB\-mpwr6\fR|\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
309: [\fB\-nops=\fR\fIcount\fR]
333: [\fB\-mint\-register=\fR\fInumber\fR]
369: [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR]
377: [\fB\-mtune=\fR\fIarch\fR]
389: [\fB\-march=\fR\fICPU\fR\fI[\-EXT]\fR\fI[+EXT]\fR]
390: [\fB\-local\-prefix=\fR\fIPREFIX\fR]
393: [\fB\-fp\-s=\fR\fIFORMAT\fR]
394: [\fB\-fp\-d=\fR\fIFORMAT\fR]
460:.IP \fB@\fR\fIfile\fR 4
557:.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4
561:.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
580:.IP \fB\-\-emulation=\fR\fIname\fR 4
645:.IP \fB\-\-gdwarf\-cie\-version=\fR\fIversion\fR 4
694:.IP \fB\-\-listing\-lhs\-width=\fR\fInumber\fR 4
698:.IP \fB\-\-listing\-lhs\-width2=\fR\fInumber\fR 4
702:.IP \fB\-\-listing\-rhs\-width=\fR\fInumber\fR 4
706:.IP \fB\-\-listing\-cont\-lines=\fR\fInumber\fR 4
820:.IP \fB\-mabi=\fR\fIabi\fR 4
825:.IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
881:.IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
909:.IP \fB\-m\fR\fIcpu\fR 4
975:.IP \fB\-G\fR\fIsize\fR 4
989:.IP \fB\-mcpu=\fR\fIcpu\fR 4
1001:.IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1004:.IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4
1007:.IP \fB\-mfpu=\fR\fIfloating-point-format\fR 4
1010:.IP \fB\-mfloat\-abi=\fR\fIabi\fR 4
1035:.IP \fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR] 4
1101:.IP \fB\-mdialect=\fR\fIdialect\fR 4
1106:.IP \fB\-misa\-spec=\fR\fIspec\fR 4
1124:.IP \fB\-march=\fR\fIarchname\fR 4
1128:.IP \fB\-mcpu=\fR\fIcpuname\fR 4
1301:.IP \fB\-mach=\fR\fIname\fR 4
1338:.IP \fB\-march=\fR\fICPU\fR\fB[+\fR\fIEXTENSION\fR\fB...]\fR 4
1532:.IP \fB\-mtune=\fR\fICPU\fR 4
1540:\&\fB\-march=\fR\fICPU\fR.
1549:.IP \fB\-msse\-check=\fR\fInone\fR 4
1552:.IP \fB\-msse\-check=\fR\fIwarning\fR 4
1554:.IP \fB\-msse\-check=\fR\fIerror\fR 4
1558:\&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check SSE
1559:instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR
1561:\&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error
1563:.IP \fB\-mavxscalar=\fR\fI128\fR 4
1566:.IP \fB\-mavxscalar=\fR\fI256\fR 4
1570:instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar
1572:\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar AVX instructions
1577:.IP \fB\-mvexwig=\fR\fI0\fR 4
1580:.IP \fB\-mvexwig=\fR\fI1\fR 4
1584:VEX instructions. \fB\-mvexwig=\fR\fI0\fR will encode WIG VEX
1586:\&\fB\-mvexwig=\fR\fI1\fR will encode WIG EVEX instructions with
1591:.IP \fB\-mevexlig=\fR\fI128\fR 4
1594:.IP \fB\-mevexlig=\fR\fI256\fR 4
1596:.IP \fB\-mevexlig=\fR\fI512\fR 4
1600:(LIG) EVEX instructions. \fB\-mevexlig=\fR\fI128\fR will encode LIG
1602:\&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will
1605:.IP \fB\-mevexwig=\fR\fI0\fR 4
1608:.IP \fB\-mevexwig=\fR\fI1\fR 4
1612:EVEX instructions. \fB\-mevexwig=\fR\fI0\fR will encode WIG
1614:\&\fB\-mevexwig=\fR\fI1\fR will encode WIG EVEX instructions with
1616:.IP \fB\-mmnemonic=\fR\fIatt\fR 4
1619:.IP \fB\-mmnemonic=\fR\fIintel\fR 4
1625:.IP \fB\-msyntax=\fR\fIatt\fR 4
1628:.IP \fB\-msyntax=\fR\fIintel\fR 4
1655:.IP \fB\-momit\-lock\-prefix=\fR\fIno\fR 4
1658:.IP \fB\-momit\-lock\-prefix=\fR\fIyes\fR 4
1665:\&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes.
1666:\&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual,
1668:.IP \fB\-mfence\-as\-lock\-add=\fR\fIno\fR 4
1671:.IP \fB\-mfence\-as\-lock\-add=\fR\fIyes\fR 4
1676:\&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and
1677:sfence as \fBlock addl \fR\f(CB$0x0\fR\fB, (%rsp)\fR in 64\-bit mode and
1678:\&\fBlock addl \fR\f(CB$0x0\fR\fB, (%esp)\fR in 32\-bit mode.
1679:\&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and
1681:.IP \fB\-mrelax\-relocations=\fR\fIno\fR 4
1684:.IP \fB\-mrelax\-relocations=\fR\fIyes\fR 4
1690:\&\fB\-mrelax\-relocations=\fR\fIyes\fR will generate relax relocations.
1691:\&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax
1694:.IP \fB\-malign\-branch\-boundary=\fR\fINUM\fR 4
1701:.IP \fB\-malign\-branch=\fR\fITYPE\fR\fB[+\fR\fITYPE\fR\fB...]\fR 4
1709:.IP \fB\-malign\-branch\-prefix\-size=\fR\fINUM\fR 4
1723:.IP \fB\-mlfence\-after\-load=\fR\fIno\fR 4
1726:.IP \fB\-mlfence\-after\-load=\fR\fIyes\fR 4
1730:after load instructions. \fB\-mlfence\-after\-load=\fR\fIyes\fR will
1731:generate lfence. \fB\-mlfence\-after\-load=\fR\fIno\fR will not generate
1733:.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR 4
1736:.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR 4
1738:.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR 4
1740:.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR 4
1745:\&\fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR will generate lfence
1748:It also implicitly sets \fB\-mlfence\-before\-ret=\fR\fIshl\fR when
1750:\&\fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR will generate
1752:\&\fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR will issue a
1754:\&\fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR will not generate
1757:\&\fB\-mlfence\-after\-load=\fR\fIyes\fR since lfence will be generated
1759:.IP \fB\-mlfence\-before\-ret=\fR\fInone\fR 4
1762:.IP \fB\-mlfence\-before\-ret=\fR\fIshl\fR 4
1764:.IP \fB\-mlfence\-before\-ret=\fR\fIor\fR 4
1766:.IP \fB\-mlfence\-before\-ret=\fR\fIyes\fR 4
1768:.IP \fB\-mlfence\-before\-ret=\fR\fInot\fR 4
1772:before ret. \fB\-mlfence\-before\-ret=\fR\fIor\fR will generate
1774:\&\fB\-mlfence\-before\-ret=\fR\fIshl/yes\fR will generate shl instruction
1775:with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not
1776:instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not
1778:.IP \fB\-mx86\-used\-note=\fR\fIno\fR 4
1781:.IP \fB\-mx86\-used\-note=\fR\fIyes\fR 4
1788:.IP \fB\-mevexrcig=\fR\fIrne\fR 4
1791:.IP \fB\-mevexrcig=\fR\fIrd\fR 4
1793:.IP \fB\-mevexrcig=\fR\fIru\fR 4
1795:.IP \fB\-mevexrcig=\fR\fIrz\fR 4
1799:EVEX instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode RC bits
1801:\&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR
1802:and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only EVEX instructions
1929:.IP \fB\-march=\fR\fIarchitecture\fR 4
2012:.IP \fB\-march=\fR\fIcpu\fR 4
2015:.IP \fB\-mtune=\fR\fIcpu\fR 4
2318:.IP \fB\-mnan=\fR\fIencoding\fR 4
2322:.IP \fB\-\-emulation=\fR\fIname\fR 4
2682:.IP \fB\-nops=\fR\fIcount\fR 4
2775:.IP \fB\-march=\fR\fIprocessor\fR 4
2797:.IP \fB\-march=\fR\fIarch\fR 4
2866:.IP \fB\-mtune=\fR\fIarch\fR 4
2939:.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
2963:.IP
\fB\-march=\fR\fICPU\fR\fB[\-\fR\fIEXT\fR\fB...][+\fR\fIEXT\fR\fB...]\fR 4
2993:.IP \fB\-local\-prefix=\fR\fIprefix\fR 4
3004:.IP \fB\-fp\-s=\fR\fIFORMAT\fR 4
3007:.IP \fB\-fp\-d=\fR\fIFORMAT\fR 4
-.-.
Use the name of units in text; use symbols in tables and
calculations.
The rule is to have a (no-break, \~) space between a number and
its units (see "www.bipm.org/en/publications/si-brochure")
1571:AVX instructions with 128bit vector length, which is the default.
1573:with 256bit vector length.
1601:EVEX instructions with 128bit vector length, which is the default.
1603:encode LIG EVEX instructions with 256bit and 512bit vector length,
-.-
SYNOPSIS: put a space on both sides of "[" and "]" to increase
readability (?)
N.B. Not in the patch
as.1:as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\fR]]
as.1: [\fB\-\-alternate\fR]
as.1: [\fB\-\-compress\-debug\-sections\fR]
[\fB\-\-nocompress\-debug\-sections\fR]
as.1: [\fB\-D\fR]
as.1: [\fB\-\-dump\-config\fR]
as.1: [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
as.1: [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
as.1: [\fB\-\-elf\-stt\-common=[no|yes]\fR]
as.1: [\fB\-\-emulation\fR=\fIname\fR]
as.1: [\fB\-f\fR]
as.1: [\fB\-g\fR] [\fB\-\-gstabs\fR] [\fB\-\-gstabs+\fR]
as.1: [\fB\-\-gdwarf\-<N>\fR] [\fB\-\-gdwarf\-sections\fR]
as.1: [\fB\-\-gdwarf\-cie\-version\fR=\fIVERSION\fR]
as.1: [\fB\-\-generate\-missing\-build\-notes=[no|yes]\fR]
as.1: [\fB\-\-gsframe\fR]
as.1: [\fB\-\-hash\-size\fR=\fIN\fR]
as.1: [\fB\-\-help\fR] [\fB\-\-target\-help\fR]
as.1: [\fB\-I\fR \fIdir\fR]
as.1: [\fB\-J\fR]
as.1: [\fB\-K\fR]
as.1: [\fB\-\-keep\-locals\fR]
as.1: [\fB\-L\fR]
as.1: [\fB\-\-listing\-lhs\-width\fR=\fINUM\fR]
as.1: [\fB\-\-listing\-lhs\-width2\fR=\fINUM\fR]
as.1: [\fB\-\-listing\-rhs\-width\fR=\fINUM\fR]
as.1: [\fB\-\-listing\-cont\-lines\fR=\fINUM\fR]
as.1: [\fB\-\-multibyte\-handling=[allow|warn|warn\-sym\-only]\fR]
as.1: [\fB\-\-no\-pad\-sections\fR]
as.1: [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR]
as.1: [\fB\-\-scfi=experimental\fR]
as.1: [\fB\-\-sectname\-subst\fR]
as.1: [\fB\-\-size\-check=[error|warning]\fR]
as.1: [\fB\-\-statistics\fR]
as.1: [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR]
as.1: [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR]
[\fB\-x\fR]
as.1: [\fB\-Z\fR] [\fB@\fR\fIFILE\fR]
as.1: [\fItarget-options\fR]
as.1: [\fB\-\-\fR|\fIfiles\fR ...]
-.-.
-- System Information:
Debian Release: trixie/sid
APT prefers testing-proposed-updates
APT policy: (500, 'testing-proposed-updates'), (500, 'testing')
Architecture: amd64 (x86_64)
Kernel: Linux 6.7.12-amd64 (SMP w/2 CPU threads; PREEMPT)
Locale: LANG=is_IS.iso88591, LC_CTYPE=is_IS.iso88591 (charmap=ISO-8859-1),
LANGUAGE not set
Shell: /bin/sh linked to /usr/bin/dash
Init: sysvinit (via /sbin/init)
-- no debconf information
