Source: mesa Followup-For: Bug #1151491 X-Debbugs-Cc: [email protected] I've now confirmed a fix with 1 revert and 2 cherry-picks from upstream:
I started from Salsa's debian/25.0.7-2, added 25.0.7-2+deb13u1 NMU changes on top, and then used: git revert 2d525d5e3401555d97fe827f8db5bfed8887dc33 # radeonsi: always lower alu bit sizes git cherry-pick f034aa9cd31ea4aa367f8ed58bd270026abf748e # radv: don't use bit_sizes_int to skip nir_lower_bit_size git cherry-pick 33b5d8b2ec26904ec1c331dd64ee04e351fd8e0e # radeonsi: always lower alu bit sizes After confirming these fix the issue I converted them to debian/patches and am including a debdiff here.
diff -Nru mesa-25.0.7/debian/changelog mesa-25.0.7/debian/changelog --- mesa-25.0.7/debian/changelog 2026-06-19 19:20:06.000000000 +0000 +++ mesa-25.0.7/debian/changelog 2026-10-20 21:31:47.000000000 +0000 @@ -1,3 +1,9 @@ +mesa (25.0.7-2+deb13u1.1) trixie; urgency=medium + + * Fix: Crash: Unsupported opcode v_lshlrev_b16 (closes #1151491) + + -- Tj <[email protected]> Tue, 20 Oct 2026 21:31:47 +0000 + mesa (25.0.7-2+deb13u1) trixie; urgency=high * Non-maintainer upload by the LTS Team. diff -Nru mesa-25.0.7/debian/patches/radeonsi_always_lower_alu_bit_sizes_v2.patch mesa-25.0.7/debian/patches/radeonsi_always_lower_alu_bit_sizes_v2.patch --- mesa-25.0.7/debian/patches/radeonsi_always_lower_alu_bit_sizes_v2.patch 1970-01-01 00:00:00.000000000 +0000 +++ mesa-25.0.7/debian/patches/radeonsi_always_lower_alu_bit_sizes_v2.patch 2026-10-20 21:31:47.000000000 +0000 @@ -0,0 +1,44 @@ +Description: radeonsi: always lower alu bit sizes +Origin: https://gitlab.freedesktop.org/mesa/mesa/-/commit/33b5d8b2ec26904ec1c331dd64ee04e351fd8e0e +Author: Georg Lehmann <[email protected]> +Date: Sun May 11 15:01:05 2025 +0200 + + radeonsi: always lower alu bit sizes + + Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13072 + + load_vs_input_from_vertex_buffer can create unsupported 16bit shifts on GFX6/7. + + Reviewed-by: Marek Olšák <[email protected]> + Reviewed-by: Qiang Yu <[email protected]> + + Cc: mesa-stable + Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34946> + +diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c +index 0c054f44bf3..4307d33cedc 100644 +--- a/src/gallium/drivers/radeonsi/si_shader.c ++++ b/src/gallium/drivers/radeonsi/si_shader.c +@@ -2553,16 +2553,15 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx * + NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes, + sel->screen->info.gfx_level, !nir->info.use_aco_amd); + +- if (nir->info.stage == MESA_SHADER_KERNEL) { ++ if (nir->info.stage == MESA_SHADER_KERNEL) + NIR_PASS(progress, nir, ac_nir_lower_global_access); + +- if (nir->info.bit_sizes_int & (8 | 16)) { +- if (sel->screen->info.gfx_level >= GFX8) +- nir_divergence_analysis(nir); ++ if (ac_nir_might_lower_bit_size(nir)) { ++ if (sel->screen->info.gfx_level >= GFX8) ++ nir_divergence_analysis(nir); + +- NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, +- &sel->screen->info.gfx_level); +- } ++ NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, ++ &sel->screen->info.gfx_level); + } + + /* This must be after lowering resources to descriptor loads and before lowering intrinsics diff -Nru mesa-25.0.7/debian/patches/radv-do-not-use-bit_sizes_int-to-skip-nir_lower_bit_size.patch mesa-25.0.7/debian/patches/radv-do-not-use-bit_sizes_int-to-skip-nir_lower_bit_size.patch --- mesa-25.0.7/debian/patches/radv-do-not-use-bit_sizes_int-to-skip-nir_lower_bit_size.patch 1970-01-01 00:00:00.000000000 +0000 +++ mesa-25.0.7/debian/patches/radv-do-not-use-bit_sizes_int-to-skip-nir_lower_bit_size.patch 2026-10-20 21:31:47.000000000 +0000 @@ -0,0 +1,117 @@ +Description: radv: don't use bit_sizes_int to skip nir_lower_bit_size +Origin: https://gitlab.freedesktop.org/mesa/mesa/-/commit/f034aa9cd31ea4aa367f8ed58bd270026abf748e +Author: Rhys Perry <[email protected]> +Date: Mon Feb 3 16:33:46 2025 +0000 + + radv: don't use bit_sizes_int to skip nir_lower_bit_size + + Signed-off-by: Rhys Perry <[email protected]> + Reviewed-by: Georg Lehmann <[email protected]> + Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29242> + +diff --git a/src/amd/common/nir/ac_nir.c b/src/amd/common/nir/ac_nir.c +index 76114ffe436..7df173a76d2 100644 +--- a/src/amd/common/nir/ac_nir.c ++++ b/src/amd/common/nir/ac_nir.c +@@ -340,11 +340,9 @@ ac_nir_optimize_uniform_atomics(nir_shader *nir) + return progress; + } + +-unsigned +-ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data) ++static unsigned ++lower_bit_size_callback(const nir_instr *instr, enum amd_gfx_level chip, bool divergence_known) + { +- enum amd_gfx_level chip = *(enum amd_gfx_level *)data; +- + if (instr->type != nir_instr_type_alu) + return 0; + nir_alu_instr *alu = nir_instr_as_alu(instr); +@@ -374,10 +372,10 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data) + case nir_op_isign: + case nir_op_uadd_sat: + case nir_op_usub_sat: +- return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; ++ return (!divergence_known || bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; + case nir_op_iadd_sat: + case nir_op_isub_sat: +- return bit_size == 8 || !alu->def.divergent ? 32 : 0; ++ return !divergence_known || bit_size == 8 || !alu->def.divergent ? 32 : 0; + + default: + return 0; +@@ -399,7 +397,7 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data) + case nir_op_uge: + case nir_op_bitz: + case nir_op_bitnz: +- return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; ++ return (!divergence_known || bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; + default: + return 0; + } +@@ -408,6 +406,28 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data) + return 0; + } + ++unsigned ++ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data) ++{ ++ enum amd_gfx_level chip = *(enum amd_gfx_level *)data; ++ return lower_bit_size_callback(instr, chip, true); ++} ++ ++bool ++ac_nir_might_lower_bit_size(const nir_shader *shader) ++{ ++ nir_foreach_function_impl(impl, shader) { ++ nir_foreach_block(block, impl) { ++ nir_foreach_instr(instr, block) { ++ if (lower_bit_size_callback(instr, CLASS_UNKNOWN, false)) ++ return true; ++ } ++ } ++ } ++ ++ return false; ++} ++ + static unsigned + align_load_store_size(enum amd_gfx_level gfx_level, unsigned size, bool uses_smem, bool is_shared) + { +diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h +index 6020015e1a1..567b8cae46a 100644 +--- a/src/amd/common/nir/ac_nir.h ++++ b/src/amd/common/nir/ac_nir.h +@@ -396,6 +396,9 @@ ac_nir_optimize_uniform_atomics(nir_shader *nir); + unsigned + ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data); + ++bool ++ac_nir_might_lower_bit_size(const nir_shader *shader); ++ + bool + ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, + unsigned num_components, int64_t hole_size, +diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c +index 46ffc0ceb06..90e7083cc61 100644 +--- a/src/amd/vulkan/radv_pipeline.c ++++ b/src/amd/vulkan/radv_pipeline.c +@@ -352,9 +352,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat + NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !instance->drirc.disable_shrink_image_store); + + constant_fold_for_push_const = true; +- +- /* Gather info again, to update whether 8/16-bit are used. */ +- nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir)); + } + } + +@@ -533,7 +530,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat + + NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64); + +- if (stage->nir->info.bit_sizes_int & (8 | 16)) { ++ if (ac_nir_might_lower_bit_size(stage->nir)) { + if (gfx_level >= GFX8) + nir_divergence_analysis(stage->nir); + diff -Nru mesa-25.0.7/debian/patches/Revert-radeonsi_always_lower_alu_bit_sizes.patch mesa-25.0.7/debian/patches/Revert-radeonsi_always_lower_alu_bit_sizes.patch --- mesa-25.0.7/debian/patches/Revert-radeonsi_always_lower_alu_bit_sizes.patch 1970-01-01 00:00:00.000000000 +0000 +++ mesa-25.0.7/debian/patches/Revert-radeonsi_always_lower_alu_bit_sizes.patch 2026-10-20 21:31:47.000000000 +0000 @@ -0,0 +1,48 @@ +Description: Revert radeonsi: always lower alu bit sizes +Author: Tj <[email protected]> +Date: Tue Oct 20 20:45:53 2026 +0000 + + Revert "radeonsi: always lower alu bit sizes" + + This reverts commit 2d525d5e3401555d97fe827f8db5bfed8887dc33. + +diff --git a/.pick_status.json b/.pick_status.json +index dae6a46eb87..d82c06d0a66 100644 +--- a/.pick_status.json ++++ b/.pick_status.json +@@ -5834,7 +5834,7 @@ + "description": "radeonsi: always lower alu bit sizes", + "nominated": true, + "nomination_type": 1, +- "resolution": 1, ++ "resolution": 0, + "main_sha": null, + "because_sha": null, + "notes": null +diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c +index 0a700863197..0c054f44bf3 100644 +--- a/src/gallium/drivers/radeonsi/si_shader.c ++++ b/src/gallium/drivers/radeonsi/si_shader.c +@@ -2553,15 +2553,16 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx * + NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes, + sel->screen->info.gfx_level, !nir->info.use_aco_amd); + +- if (nir->info.stage == MESA_SHADER_KERNEL) ++ if (nir->info.stage == MESA_SHADER_KERNEL) { + NIR_PASS(progress, nir, ac_nir_lower_global_access); + +- if (nir->info.bit_sizes_int & (8 | 16)) { +- if (sel->screen->info.gfx_level >= GFX8) +- nir_divergence_analysis(nir); ++ if (nir->info.bit_sizes_int & (8 | 16)) { ++ if (sel->screen->info.gfx_level >= GFX8) ++ nir_divergence_analysis(nir); + +- NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, +- &sel->screen->info.gfx_level); ++ NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, ++ &sel->screen->info.gfx_level); ++ } + } + + /* This must be after lowering resources to descriptor loads and before lowering intrinsics diff -Nru mesa-25.0.7/debian/patches/series mesa-25.0.7/debian/patches/series --- mesa-25.0.7/debian/patches/series 2026-06-19 19:20:06.000000000 +0000 +++ mesa-25.0.7/debian/patches/series 2026-10-20 21:31:47.000000000 +0000 @@ -7,3 +7,6 @@ backport_STACK_ARRAY.patch CVE-2026-40393-part1.patch CVE-2026-40393-part2.patch +Revert-radeonsi_always_lower_alu_bit_sizes.patch +radv-do-not-use-bit_sizes_int-to-skip-nir_lower_bit_size.patch +radeonsi_always_lower_alu_bit_sizes_v2.patch
