I added the memory barrier instructions and the JRE appears to be working. Here is the patch:
--- cacao-0.99.4/src/vm/jit/mips/md-atomic.hpp~ 2009-08-27 15:30:44.000000000 -0400 +++ cacao-0.99.4/src/vm/jit/mips/md-atomic.hpp 2009-08-27 13:13:07.000000000 -0400 @@ -127,12 +127,12 @@ */ inline static void Atomic_memory_barrier(void) { - __asm__ __volatile__ ("" : : : "memory"); + __asm__ __volatile__ (".set mips64; sync; .set mips0" : : : "memory"); } -#define STORE_ORDER_BARRIER() __asm__ __volatile__ ("" : : : "memory"); -#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("" : : : "memory"); +#define STORE_ORDER_BARRIER() __asm__ __volatile__ (".set mips64; sync; .set mips0" : : : "memory"); +#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ (".set mips64; sync; .set mips0" : : : "memory"); #endif // _MD_ATOMIC_HPP I suspect that the above may not be optimal -- I think that the hardware I have (OCTEON CN5650-NSP pass 2.1, 12 CPUs at 600 MHz) does not require read barriers. Someone with more expertise is needed to tune this. -- To UNSUBSCRIBE, email to debian-bugs-dist-requ...@lists.debian.org with a subject of "unsubscribe". Trouble? Contact listmas...@lists.debian.org