Package: cpuid
Version: 3.3-9
Severity: wishlist
Tags: patch
Hi,
thanks for maintaining cpuid. As I've been curious to find out wether my
processor supports nested page tables, I found that cpuid didn't check for
that bit yet. I've added that and did a few corrections/extensions to the
current AMD CPUID Specification (Revision 2.28) in the attached patch.
To verify the results I've also tested this on two AMD systems, output is
also attached.
Cheers and thanks in advance,
Stefan.
-- System Information:
Debian Release: squeeze/sid
APT prefers unstable
APT policy: (500, 'unstable'), (1, 'experimental')
Architecture: amd64 (x86_64)
Kernel: Linux 2.6.32-5-amd64 (SMP w/4 CPU cores)
Locale: LANG=de_DE.UTF-8, LC_CTYPE=de_DE.UTF-8 (charmap=UTF-8)
Shell: /bin/sh linked to /bin/dash
Versions of packages cpuid depends on:
ii libc6 2.11.2-2 Embedded GNU C Library: Shared lib
cpuid recommends no packages.
cpuid suggests no packages.
-- no debconf information
--- cpuid.c.orig 2002-01-02 07:14:51.000000000 +0100
+++ cpuid.c 2010-07-24 13:23:05.341662973 +0200
@@ -21,7 +21,7 @@
void printregs(int eax,int ebx,int ecx,int edx);
#define MAXBRANDS 9
-char *Brands[MAXBRANDS] = {
+static const char *Brands[MAXBRANDS] = {
"brand 0",
"Celeron processor",
"Pentium III processor",
@@ -89,7 +89,7 @@
exit(0);
}
-char *Intel_feature_flags[] = {
+static const char *Intel_feature_flags[] = {
"FPU Floating Point Unit",
"VME Virtual 8086 Mode Enhancements",
"DE Debugging Extensions",
@@ -491,42 +491,117 @@
break;
}
}
-char *AMD_feature_flags[] = {
- "Floating Point Unit",
- "Virtual Mode Extensions",
- "Debugging Extensions",
- "Page Size Extensions",
- "Time Stamp Counter (with RDTSC and CR4 disable bit)",
- "Model Specific Registers with RDMSR & WRMSR",
- "PAE - Page Address Extensions",
- "Machine Check Exception",
- "COMPXCHG8B Instruction",
- "APIC",
- "10 - Reserved",
- "SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions",
- "MTRR - Memory Type Range Registers",
- "Global paging extension",
- "Machine Check Architecture",
- "Conditional Move Instruction",
- "PAT - Page Attribute Table",
- "PSE-36 - Page Size Extensions",
- "18 - reserved",
- "19 - reserved",
- "20 - reserved",
- "21 - reserved",
- "AMD MMX Instruction Extensions",
- "MMX instructions",
- "FXSAVE/FXRSTOR",
- "25 - reserved",
- "26 - reserved",
- "27 - reserved",
- "28 - reserved",
- "29 - reserved",
- "3DNow! Instruction Extensions",
- "3DNow instructions",
+
+/* flags for function 0000 0001, edx */
+static const char *AMD_feature_flags[] = {
+ "Floating Point Unit", /* 0 */
+ "Virtual Mode Extensions", /* 1 */
+ "Debugging Extensions", /* 2 */
+ "Page Size Extensions", /* 3 */
+ "Time Stamp Counter (with RDTSC and CR4 disable bit)", /* 4 */
+ "Model Specific Registers with RDMSR & WRMSR", /* 5 */
+ "PAE - Page Address Extensions", /* 6 */
+ "Machine Check Exception", /* 7 */
+ "COMPXCHG8B Instruction", /* 8 */
+ "APIC", /* 0 */
+ "10 - Reserved", /* 10 */
+ "SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions", /* 11 */
+ "MTRR - Memory Type Range Registers", /* 12 */
+ "Global paging extension", /* 13 */
+ "Machine Check Architecture", /* 14 */
+ "Conditional Move Instruction", /* 15 */
+ "PAT - Page Attribute Table", /* 16 */
+ "PSE-36 - Page Size Extensions", /* 17 */
+ "18 - reserved", /* 18 */
+ "CLFLUSH instruction", /* 19 */
+ "20 - reserved", /* 20 */
+ "21 - reserved", /* 21 */
+ "22 - reserved", /* 22 */
+ "MMX instructions", /* 23 */
+ "FXSAVE/FXRSTOR", /* 24 */
+ "SSE Extensions", /* 25 */
+ "SSE2 Extensions", /* 26 */
+ "27 - reserved", /* 27 */
+ "HTT: hyperthreading technology", /* 28 */
+ "29 - reserved", /* 29 */
+ "30 - reserved", /* 30 */
+ "31 - reserved", /* 31 */
+};
+
+/* flags for function 8000 0001, edx */
+static const char *AMD_feature_flags_80000001_edx[] = {
+ "Floating Point Unit", /* 0 */
+ "Virtual Mode Extensions", /* 1 */
+ "Debugging Extensions", /* 2 */
+ "Page Size Extensions", /* 3 */
+ "Time Stamp Counter (with RDTSC and CR4 disable bit)", /* 4 */
+ "Model Specific Registers with RDMSR & WRMSR", /* 5 */
+ "PAE - Page Address Extensions", /* 6 */
+ "Machine Check Exception", /* 7 */
+ "COMPXCHG8B Instruction", /* 8 */
+ "APIC", /* 0 */
+ "10 - Reserved", /* 10 */
+ "SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions", /* 11 */
+ "MTRR - Memory Type Range Registers", /* 12 */
+ "Global paging extension", /* 13 */
+ "Machine Check Architecture", /* 14 */
+ "Conditional Move Instruction", /* 15 */
+ "PAT - Page Attribute Table", /* 16 */
+ "PSE-36 - Page Size Extensions", /* 17 */
+ "18 - reserved", /* 18 */
+ "19 - reserved", /* 19 */
+ "NX - No execute page protection", /* 20 */
+ "21 - reserved", /* 21 */
+ "MMXext - AMD extensions to MMX instructions", /* 22 */
+ "MMX instructions", /* 23 */
+ "FXSAVE/FXRSTOR", /* 24 */
+ "FFXSR: FXSAVE/FXRSTOR instruction optimizations", /* 25 */
+ "1 GB large page support", /* 26 */
+ "RDTSCP", /* 27 */
+ "28 - reserved", /* 28 */
+ "LM: Long mode", /* 29 */
+ "3DNow! Instruction Extensions", /* 30 */
+ "3DNOW! instructions", /* 31 */
+};
+
+/* flags for function 8000 0001, ecx */
+static const char *AMD_feature_flags_80000001_ecx[] = {
+ "LahfSahf - LAHF and SAHF instructions in 64 bit mode", /* 0 */
+ "CmpLegacy - core multiprocessing legacy mode", /* 1 */
+ "SVM - secure virtual machine", /* 2 */
+ "ExtApic - extended APIC space", /* 3 */
+ "AltMovCR8 - LOCK MOV CR0 means MOV CR8", /* 4 */
+ "ABM - advanced bit manipulation: LZCNT instruction", /* 5 */
+ "SSE4A - EXTRQ INSERTQ MOVNTSS MOVNTSD", /* 6 */
+ "MisAlignSse - misaligned sse mode", /* 7 */
+ "3DNowPrefetch - PREFETCH PREFETCHW", /* 8 */
+ "OSVW - OS visible workaround", /* 9 */
+ "IBS - Instruction based sampling", /* 10 */
+ "SSE5", /* 11 */
+ "SKINIT - SKINIT STGI", /* 12 */
+ "WDT - Watchdog timer support", /* 13 */
+ "14 - reserved", /* 14 */
+ "15 - reserved", /* 15 */
+ "16 - reserved", /* 16 */
+ "17 - reserved", /* 17 */
+ "18 - reserved", /* 18 */
+ "19 - reserved", /* 19 */
+ "20 - reserved", /* 20 */
+ "21 - reserved", /* 21 */
+ "22 - reserved", /* 22 */
+ "23 - reserved", /* 23 */
+ "24 - reserved", /* 24 */
+ "25 - reserved", /* 25 */
+ "26 - reserved", /* 26 */
+ "27 - reserved", /* 27 */
+ "28 - reserved", /* 28 */
+ "29 - reserved", /* 29 */
+ "30 - reserved", /* 30 */
+ "31 - reserved", /* 31 */
};
-char *Assoc[] = {
+
+static const char *Assoc[] = {
"L2 off",
"Direct mapped",
"2-way",
@@ -551,6 +626,7 @@
void doamd(int maxi){
unsigned long maxei,unused;
int family = 0;
+ int have_svm = 0;
printf("AMD-specific functions\n");
@@ -657,10 +733,16 @@
printf("Global Paging Extensions\n");
} else {
if(edx & (1<<i)){
- printf("%s\n",AMD_feature_flags[i]);
+ printf("%s\n",AMD_feature_flags_80000001_edx[i]);
}
}
}
+ for(i=0;i<32;i++){
+ if(ecx & (1<<i)){
+ printf("%s\n",AMD_feature_flags_80000001_ecx[i]);
+ }
+ }
+ have_svm = (ecx & (1 << 2));
}
printf("\n");
if(maxei >= 0x80000002){
@@ -754,6 +836,30 @@
printf("Maximum linear address: %ld; maximum phys address %ld\n",
(eax>>8) & 0xff,eax&0xff);
}
+ /* 8000000a: svm revision and feature identification
+ * (reserved, if svm is not present) */
+ if((maxei >= 0x8000000a) && have_svm) {
+ unsigned long eax, ebx, reserved, edx;
+ cpuid(0x8000000a,eax,ebx,reserved,edx);
+ /* eax: 31:8 reserved, 7:0 svm revision */
+ printf("SVM revision: %ld\n", eax & 0xff);
+ printf(" NASID: Number of Address space identifiers %ld\n", ebx);
+ if(edx & (1 << 0)) {
+ printf(" NP: Nested paging\n");
+ }
+ if(edx & (1 << 1)) {
+ printf(" LbrVirt: LBR Virtualisation\n");
+ }
+ if(edx & (1 << 2)) {
+ printf(" SVM Lock\n");
+ }
+ if(edx & (1 << 3)) {
+ printf(" NRIPS: NRIP Save\n");
+ }
+ if(edx & (1 << 9)) {
+ printf(" SSE3 and SSE5 opcode disable\n");
+ }
+ }
}
char *Cyrix_standard_feature_flags_5[] = {
eax in eax ebx ecx edx
00000000 00000005 68747541 444d4163 69746e65
00000001 00100f42 00040800 00802009 178bfbff
00000002 00000000 00000000 00000000 00000000
00000003 00000000 00000000 00000000 00000000
00000004 00000000 00000000 00000000 00000000
00000005 00000040 00000040 00000003 00000000
80000000 8000001b 68747541 444d4163 69746e65
80000001 00100f42 10001857 000037ff efd3fbff
80000002 20444d41 6e656850 74286d6f 4920296d
80000003 34582049 35303920 72502065 7365636f
80000004 00726f73 00000000 00000000 00000000
80000005 ff30ff10 ff30ff20 40020140 40020140
80000006 20800000 42004200 02008140 0030b140
80000007 00000000 00000000 00000000 000001f9
80000008 00003030 00000000 00002003 00000000
80000009 00000000 00000000 00000000 00000000
8000000a 00000001 00000040 00000000 0000000f
8000000b 00000000 00000000 00000000 00000000
8000000c 00000000 00000000 00000000 00000000
8000000d 00000000 00000000 00000000 00000000
8000000e 00000000 00000000 00000000 00000000
8000000f 00000000 00000000 00000000 00000000
80000010 00000000 00000000 00000000 00000000
80000011 00000000 00000000 00000000 00000000
80000012 00000000 00000000 00000000 00000000
80000013 00000000 00000000 00000000 00000000
80000014 00000000 00000000 00000000 00000000
80000015 00000000 00000000 00000000 00000000
80000016 00000000 00000000 00000000 00000000
80000017 00000000 00000000 00000000 00000000
80000018 00000000 00000000 00000000 00000000
80000019 f0300000 60100000 00000000 00000000
8000001a 00000003 00000000 00000000 00000000
8000001b 0000001f 00000000 00000000 00000000
Vendor ID: "AuthenticAMD"; CPUID level 5
AMD-specific functions
Version 00100f42:
Family: 15 Model: 4 []
Standard feature flags 178bfbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
19 - reserved
MMX instructions
FXSAVE/FXRSTOR
25 - reserved
26 - reserved
28 - reserved
Generation: 15 Model: 4
Extended feature flags efd3fbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
20 - reserved
AMD MMX Instruction Extensions
MMX instructions
FXSAVE/FXRSTOR
25 - reserved
26 - reserved
27 - reserved
29 - reserved
3DNow! Instruction Extensions
3DNow instructions
Processor name string: AMD Phenom(tm) II X4 905e Processor
L1 Cache Information:
2/4-MB Pages:
Data TLB: associativity 255-way #entries 48
Instruction TLB: associativity 255-way #entries 16
4-KB Pages:
Data TLB: associativity 255-way #entries 48
Instruction TLB: associativity 255-way #entries 32
L1 Data cache:
size 64 KB associativity 2-way lines per tag 1 line size 64
L1 Instruction cache:
size 64 KB associativity 2-way lines per tag 1 line size 64
L2 Cache Information:
2/4-MB Pages:
Data TLB: associativity L2 off #entries 128
Instruction TLB: associativity L2 off #entries 0
4-KB Pages:
Data TLB: associativity 2-way #entries 0
Instruction TLB: associativity 2-way #entries 0
size 2 KB associativity L2 off lines per tag 129 line size 64
Advanced Power Management Feature Flags
Has temperature sensing diode
Maximum linear address: 48; maximum phys address 48
eax in eax ebx ecx edx
00000000 00000001 68747541 444d4163 69746e65
00000001 00060fb2 01020800 00002001 178bfbff
80000000 80000018 68747541 444d4163 69746e65
80000001 00060fb2 000008df 0000011f ebd3fbff
80000002 20444d41 6c687441 74286e6f 3620296d
80000003 32582034 61754420 6f43206c 50206572
80000004 65636f72 726f7373 30363520 00002b30
80000005 ff08ff08 ff20ff20 40020140 40020140
80000006 00000000 42004200 02008140 00000000
80000007 00000000 00000000 00000000 0000007f
80000008 00003028 00000000 00000001 00000000
80000009 00000000 00000000 00000000 00000000
8000000a 00000001 00000040 00000000 00000002
8000000b 00000000 00000000 00000000 00000000
8000000c 00000000 00000000 00000000 00000000
8000000d 00000000 00000000 00000000 00000000
8000000e 00000000 00000000 00000000 00000000
8000000f 00000000 00000000 00000000 00000000
80000010 00000000 00000000 00000000 00000000
80000011 00000000 00000000 00000000 00000000
80000012 00000000 00000000 00000000 00000000
80000013 00000000 00000000 00000000 00000000
80000014 00000000 00000000 00000000 00000000
80000015 00000000 00000000 00000000 00000000
80000016 00000000 00000000 00000000 00000000
80000017 00000000 00000000 00000000 00000000
80000018 00000000 00000000 00000000 00000000
Vendor ID: "AuthenticAMD"; CPUID level 1
AMD-specific functions
Version 00060fb2:
Family: 15 Model: 11 []
Standard feature flags 178bfbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
CLFLUSH instruction
MMX instructions
FXSAVE/FXRSTOR
SSE Extensions
SSE2 Extensions
HTT: hyperthreading technology
Generation: 15 Model: 11
Extended feature flags ebd3fbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
NX - No execute page protection
MMXext - AMD extensions to MMX instructions
MMX instructions
FXSAVE/FXRSTOR
FFXSR: FXSAVE/FXRSTOR instruction optimizations
RDTSCP
LM: Long mode
3DNow! Instruction Extensions
3DNOW! instructions
LahfSahf - LAHF and SAHF instructions in 64 bit mode
CmpLegacy - core multiprocessing legacy mode
SVM - secure virtual machine
ExtApic - extended APIC space
AltMovCR8 - LOCK MOV CR0 means MOV CR8
3DNowPrefetch - PREFETCH PREFETCHW
Processor name string: AMD Athlon(tm) 64 X2 Dual Core Processor 5600+
L1 Cache Information:
2/4-MB Pages:
Data TLB: associativity 255-way #entries 8
Instruction TLB: associativity 255-way #entries 8
4-KB Pages:
Data TLB: associativity 255-way #entries 32
Instruction TLB: associativity 255-way #entries 32
L1 Data cache:
size 64 KB associativity 2-way lines per tag 1 line size 64
L1 Instruction cache:
size 64 KB associativity 2-way lines per tag 1 line size 64
L2 Cache Information:
2/4-MB Pages:
Data TLB: associativity L2 off #entries 0
Instruction TLB: associativity L2 off #entries 0
4-KB Pages:
Data TLB: associativity 2-way #entries 0
Instruction TLB: associativity 2-way #entries 0
size 2 KB associativity L2 off lines per tag 129 line size 64
Advanced Power Management Feature Flags
Has temperature sensing diode
Supports Frequency ID control
Supports Voltage ID control
Maximum linear address: 48; maximum phys address 40
SVM revision: 1
NASID: Number of Address space identifiers 64
LbrVirt: LBR Virtualisation
