reassign 524003 linux-2.6 2.6.32-5 tags 524003 - help thanks. * Pierre Habouzit | 2009-04-15 01:40:32 [+0200]:
>Hi Mikio, I'm the Debian maintainer of tokyocabinet, I wanted to report >to you that tokyocabinet seems to have issues on armel (and also hppa). >You can see the full build logs here: >https://buildd.debian.org/fetch.cgi?pkg=tokyocabinet&arch=armel&ver=1.4.14-2&stamp=1239676884&file=log&as=raw >https://buildd.debian.org/fetch.cgi?pkg=tokyocabinet&arch=hppa&ver=1.4.14-2&stamp=1239662413&file=log&as=raw I've been looking at the ARM part and I can reproduce this here on my machine. The error message or that part where the test case stopped depends very much on the seed. With seed=0 or 1 (don't remember really) I got an infinite loop. So it looked to me for a while that the test code is buggy. Also comparing the seed with amd64 the armel seed is much higher. However nothing of this true :) I looks now that this a kernel bug. The patch at [0] which I attached seems to fix the issue and I was able to build the package on my arm box after applying the patch. I would be happy if someone could re-test this on ARM and on HPPA. I reassing to package to the kernel team since I thing the user space is fine. I don't patch tag since the two dcache flushes don't look right and upstream did not apply it yet. We will see. Date: Thu, 21 Jan 2010 13:07:57 +0800 Message-ID: <979dd0561001202107v4ddc1eb7xa59a7c16c452f...@mail.gmail.com> Subject: [PATCH] Flush dcache before writing into page to avoid alias From: anfei zhou <anfei.z...@gmail.com> To: linux...@kvack.org, linux-ker...@vger.kernel.org Cc: Andrew Morton <a...@linux-foundation.org>, KOSAKI Motohiro <kosaki.motoh...@jp.fujitsu.com>, li...@arm.linux.org.uk, Jamie Lokier <ja...@shareable.org> Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-ow...@vger.kernel.org Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> The cache alias problem will happen if the changes of user shared mapping is not flushed before copying, then user and kernel mapping may be mapped into two different cache line, it is impossible to guarantee the coherence after iov_iter_copy_from_user_atomic. So the right steps should be: flush_dcache_page(page); kmap_atomic(page); write to page; kunmap_atomic(page); flush_dcache_page(page); More precisely, we might create two new APIs flush_dcache_user_page and flush_dcache_kern_page to replace the two flush_dcache_page accordingly. Here is a snippet tested on omap2430 with VIPT cache, and I think it is not ARM-specific: int val = 0x11111111; fd = open("abc", O_RDWR); addr = mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); *(addr+0) = 0x44444444; tmp = *(addr+0); *(addr+1) = 0x77777777; write(fd, &val, sizeof(int)); close(fd); The results are not always 0x11111111 0x77777777 at the beginning as expected. Signed-off-by: Anfei <anfei.z...@gmail.com> --- fs/fuse/file.c | 3 +++ mm/filemap.c | 3 +++ 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/fs/fuse/file.c b/fs/fuse/file.c index c18913a..a9f5e13 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -828,6 +828,9 @@ static ssize_t fuse_fill_write_pages(struct fuse_req *req, if (!page) break; + if (mapping_writably_mapped(mapping)) + flush_dcache_page(page); + pagefault_disable(); tmp = iov_iter_copy_from_user_atomic(page, ii, offset, bytes); pagefault_enable(); diff --git a/mm/filemap.c b/mm/filemap.c index 96ac6b0..07056fb 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -2196,6 +2196,9 @@ again: if (unlikely(status)) break; + if (mapping_writably_mapped(mapping)) + flush_dcache_page(page); + pagefault_disable(); copied = iov_iter_copy_from_user_atomic(page, i, offset, bytes); pagefault_enable(); -- 1.6.3.1 [0] http://lkml.org/lkml/2010/1/21/3 Sebastian -- To UNSUBSCRIBE, email to debian-bugs-rc-requ...@lists.debian.org with a subject of "unsubscribe". Trouble? Contact listmas...@lists.debian.org
