On 2010/03/23 18:21, "Raphael Hertzog" <[email protected]> wrote: > On Tue, 23 Mar 2010, Kyle Moffett wrote: >> It has the unfortunate GNU arch triplet of "powerpc-linux-gnuspe", when >> it should have been "powerpcspe-linux-gnu" or "e500-linux-gnu". This >> causes much the same problem and has the same solution as the lpia >> architecture's triplet: "arm-linux-gnulp". The result is a few extra >> entries in the "ostable" file to deal with the quirk. > > We already got a bugreport about this: http://bugs.debian.org/568123
Ah, my apologies. I'd actually already seen that one, but wasn't paying enough attention when submitting the bugreport. > The suggested names were different, your input in the discussion is > certainly welcome so that the name can be defined once for all. > > e500 might not be a very wise name if it refers to a specific product > rather than a processor family. The "spe" in the arch triplet refers to the set of extensions to the PowerPC/POWER instruction set that are implemented by the MPC85xx-series processors. The e500-series cores themselves conform to Power ISA v.2.03, but the particular implementation of floating-point support is quirky enough that it requires a separate ABI. The Wikipedia page is particularly enlightening: http://en.wikipedia.org/wiki/PowerPC_e500 Currently Freescale is the only company that makes processors which have support for the SPE/"Signal Processing Engine" instructions (all of those cores are referred to with the designator "e500"). The core reference manual indicates: http://www.phxmicro.com/CourseNotes/E500CORERM_rev1.pdf The SPE APU and embedded floating-point APU functionality is implemented in all PowerQUICC III devices. However, these instructions will not be supported in devices subsequent to PowerQUICC III. Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers. Customer software that uses SPE or embedded floating-point APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. So while it is theoretically conceivable that a processor core series other than the e500 would support the "SPE" instruction set, it is unlikely. In the event that something like that occurs however, it would be no different technically from the "amd64" or "i386" architectures. Neither of those names are even remotely accurate today yet they are commonly understood. Unfortunately, for processors which implement the "SPE" instruction set there is no other hardware support for floating point. As a result, efficient operation on these processors virtually requires a separate architecture port. So it is my belief that "e500" is the correct and appropriate name for the architecture. To be blatantly honest, I personally would really prefer if that's the final name as it would save me about 3 days worth of re-bootstrapping packages using a different architecture token. If you all think something else is definitely more appropriate I will however defer to your judgment (with some amount of grumbling and complaining). Cheers, Kyle Moffett -- Kyle Moffett eXMeritus Software Integrated Intelligence The Boeing Company (703) 764-0925 (703) 832-0657 (fax) [email protected] -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". Trouble? Contact [email protected]
