Benjamin Herrenschmidt writes:
> From my quick tests here (I'm travelling, so no much time), it looks
> like it's dying on the first msleep() (either radeonfb or whatever else
> if you play with driver order), which makes me strongly suspect the idle
> loop changes. I'll try to fix that when I'm back next week unless paulus
> beats me to it.
This patch fixes it for me on my powerbook (1.5GHz albook). The issue
seems to be that the cpu objects to HID0_NAP being cleared in HID0.
If I have this code power_save_6xx_restore, it hangs:
_GLOBAL(power_save_6xx_restore)
mfspr r11,SPRN_HID0
rlwinm r11,r11,0,10,8 /* Clear NAP */
mtspr SPRN_HID0,r11
b transfer_to_handler_cont
If I take out that rlwinm, it boots. Bizaare.
Paul.
diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 12a4efb..99e0356 100644
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -157,35 +157,32 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
/*
* Return from NAP/DOZE mode, restore some CPU specific registers,
* we are called with DR/IR still off and r2 containing physical
- * address of current.
+ * address of current. R11 and CR contain HID0. We have to preserve
+ * r10 and r12.
*/
_GLOBAL(power_save_6xx_restore)
- mfspr r11,SPRN_HID0
- rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */
- cror 4*cr1+eq,4*cr0+eq,4*cr0+eq
-BEGIN_FTR_SECTION
- rlwinm r11,r11,0,9,7 /* Clear DOZE */
-END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
- mtspr SPRN_HID0, r11
-
#ifdef DEBUG
- beq cr1,1f
+ bf 9,1f
lis r11,(nap_return_count-KERNELBASE)@ha
lwz r9,[EMAIL PROTECTED](r11)
addi r9,r9,1
stw r9,[EMAIL PROTECTED](r11)
1:
#endif
-
+
+#ifdef CONFIG_SMP
rlwinm r9,r1,0,0,18
tophys(r9,r9)
lwz r11,TI_CPU(r9)
slwi r11,r11,2
+#else
+ li r11,0
+#endif
/* Todo make sure all these are in the same page
- * and load r22 (@ha part + CPU offset) only once
+ * and load r11 (@ha part + CPU offset) only once
*/
BEGIN_FTR_SECTION
- beq cr1,1f
+ bf 9,1f
addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha
lwz r9,[EMAIL PROTECTED](r9)
mtspr SPRN_MSSCR0, r9
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