Becky Bruce writes:
> Actually, I think the problem is that the code linux is using to turn
> on nap mode is not guaranteed to put the processor in nap mode by the
> time the blr in ppc6xx_idle occurs.
Thanks, Becky.
This patch fixes it for me. Comments, anyone?
Paul.
diff -urN powerpc-merge/arch/powerpc/kernel/idle_6xx.S
pmac-2.6.17-rc1/arch/powerpc/kernel/idle_6xx.S
--- powerpc-merge/arch/powerpc/kernel/idle_6xx.S 2006-04-04
23:09:16.000000000 -0700
+++ pmac-2.6.17-rc1/arch/powerpc/kernel/idle_6xx.S 2006-04-14
10:29:54.000000000 -0700
@@ -151,41 +151,47 @@
isync
mtmsr r7
isync
- sync
- blr
+1: b 1b
/*
* Return from NAP/DOZE mode, restore some CPU specific registers,
* we are called with DR/IR still off and r2 containing physical
- * address of current.
+ * address of current. R11 and CR contain HID0. We have to preserve
+ * r10 and r12.
*/
_GLOBAL(power_save_6xx_restore)
+ tophys(r11, r1) /* Make the idle task do a blr */
+ lwz r9,_LINK(r11)
+ stw r9,_NIP(r11)
mfspr r11,SPRN_HID0
- rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */
- cror 4*cr1+eq,4*cr0+eq,4*cr0+eq
+ rlwinm r11,r11,0,10,8 /* Clear NAP */
BEGIN_FTR_SECTION
rlwinm r11,r11,0,9,7 /* Clear DOZE */
END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
mtspr SPRN_HID0, r11
#ifdef DEBUG
- beq cr1,1f
+ bf 9,1f
lis r11,(nap_return_count-KERNELBASE)@ha
lwz r9,[EMAIL PROTECTED](r11)
addi r9,r9,1
stw r9,[EMAIL PROTECTED](r11)
1:
#endif
-
+
+#ifdef CONFIG_SMP
rlwinm r9,r1,0,0,18
tophys(r9,r9)
lwz r11,TI_CPU(r9)
slwi r11,r11,2
+#else
+ li r11,0
+#endif
/* Todo make sure all these are in the same page
- * and load r22 (@ha part + CPU offset) only once
+ * and load r11 (@ha part + CPU offset) only once
*/
BEGIN_FTR_SECTION
- beq cr1,1f
+ bf 9,1f
addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha
lwz r9,[EMAIL PROTECTED](r9)
mtspr SPRN_MSSCR0, r9
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