Le 01/07/21 à 21:03, BERTRAND Joël <joel.bertr...@systella.fr> a écrit : > Je ne me souviens pas, mais quelle est la taille de la mémoire > graphique sur la machine en question ?
Aucune idée… Comment je peux voir ça ? > Ça vaut le coup d'augmenter la taille pour voir si cela change quelque chose. J'ai fouillé tous les paramètres du bios en mode avancé mais rien trouvé qui me permette de choisir ça. Vu que c'est le chipset vidéo embarqué sur le CPU qui gère ça, il se sert pas tout seul dans la RAM en fonction de ses besoins ? C'est ce processeur https://ark.intel.com/content/www/us/en/ark/products/196603/intel-core-i5-1035g1-processor-6m-cache-up-to-3-60-ghz.html Dans ses specs (pdf "10th Gen Intel® Core™ Processor Families Datasheet, Volume 2 of 2" récupéré sur cette page) on peut lire ce qui suit (qui me cause pas vraiment) 2.9 Graphics Memory Address Ranges The integrated memory controller can be programmed to direct memory accesses to the Processor Graphics when addresses are within any of the ranges specified using registers in MCH Device 2 configuration space. • The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated using the graphics translation table. • The Graphics Translation Table Base Register (GTTADR) is used to access the translation table and graphics control registers. This is part of the GTTMMADR register. These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC address ranges. They should reside above the top of memory (TOLUD) and below 4 GB so they do not take any physical DRAM memory space. Alternatively, these ranges can reside above 4 GB, similar to other BARs that are larger than 32 bits in size. GMADR is a Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. 2.9.1 IOBAR Mapped Access to Device 2 MMIO Space Device 2, Processor Graphics, contains an IOBAR register. If Device 2 is enabled, Processor Graphics registers or the GTT table can be accessed using this IOBAR. The IOBAR is composed of an index register and a data register. MMIO_Index: MMIO_INDEX is a 32-bit register. A 32-bit (all bytes enabled) I/O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed. An I/O Read returns the current value of this register. I/O read/write accesses less than 32 bits in size (all bytes enabled) will not target this register. MMIO_Data: MMIO_DATA is a 32-bit register. A 32-bit (all bytes enabled) I/O write to this port is re-directed to the MMIO register pointed to by the MMIO-index register. An I/O read to this port is re-directed to the MMIO register pointed to by the MMIO-index register. I/O read/write accesses less than 32 bits in size (all bytes enabled) will not target this register. The result of accesses through IOBAR can be: • Accesses directed to the GTT table. (that is, route to DRAM) • Accesses to Processor Graphics registers with the device. • Accesses to Processor Graphics display registers now located within the PCH. (that is, route to DMI). Note: GTT table space writes (GTTADR) are supported through this mapping mechanism. This mechanism to access Processor Graphics MMIO registers should NOT be used to access VGA I/O registers that are mapped through the MMIO space. VGA registers should be accessed directly through the dedicated VGA I/O ports. 2.9.2 Trusted Graphics Ranges Trusted graphics ranges are NOT supported. -- Daniel Les Etats-Unis sont le seul pays à être passé de la barbarie à la décadence sans connaître la civilisation. Albert Einstein.