debian/changelog | 13 + debian/patches/add-known-hsw-names.diff | 60 ++++++ debian/patches/add-more-correct-hsw-names.diff | 73 ++++++++ debian/patches/add-more-reserved-hsw-ids.diff | 204 +++++++++++++++++++++++ debian/patches/add-reserved-hsw-ids.diff | 107 ++++++++++++ debian/patches/add-vlv-ids.diff | 36 ++++ debian/patches/fix-hsw-crw-ids.diff | 40 ++++ debian/patches/fix-hsw-gt3-names.diff | 217 +++++++++++++++++++++++++ debian/patches/series | 7 9 files changed, 757 insertions(+)
New commits: commit bf78fc9f86e56c6ef58373311d574fc1e377e214 Author: Maarten Lankhorst <maarten.lankho...@canonical.com> Date: Wed Jun 19 11:14:12 2013 +0200 Added patches to add/fix Haswell pci-id's (LP: #1175533) add-reserved-hsw-ids.diff fix-hsw-gt3-names.diff add-more-reserved-hsw-ids.diff add-known-hsw-names.diff add-more-correct-hsw-names.diff (cherry picked from commit a7810f2743cafcf6ff4b4ee74280978d89a50637) Conflicts: debian/patches/series Added: add-vlv-ids.diff fix-hsw-crw-ids.diff diff --git a/debian/changelog b/debian/changelog index e268888..aafe89e 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,16 @@ +xserver-xorg-video-intel (2:2.20.9-0ubuntu2.2) UNRELEASED; urgency=low + + * Added patches to add/fix Haswell pci-id's (LP: #1175533) + - add-vlv-ids.diff + - fix-hsw-crw-ids.diff + - add-reserved-hsw-ids.diff + - fix-hsw-gt3-names.diff + - add-more-reserved-hsw-ids.diff + - add-known-hsw-names.diff + - add-more-correct-hsw-names.diff + + -- Maarten Lankhorst <maarten.lankho...@ubuntu.com> Wed, 19 Jun 2013 11:12:48 +0200 + xserver-xorg-video-intel (2:2.20.9-0ubuntu2.1) quantal-proposed; urgency=low * debian/xserver-xorg-video-intel.udev: Drop udev rule for gpu lockup diff --git a/debian/patches/add-known-hsw-names.diff b/debian/patches/add-known-hsw-names.diff new file mode 100644 index 0000000..8c4fecd --- /dev/null +++ b/debian/patches/add-known-hsw-names.diff @@ -0,0 +1,60 @@ +commit b507796679529b14c99e8937870561cd8eebebb9 +Author: Chris Wilson <ch...@chris-wilson.co.uk> +Date: Tue May 28 12:13:02 2013 +0100 + + Add the known marketing names for the performance Haswell parts + + Start filling in the names for the parts that have been announced, the + Iris branded Haswell GT3 parts. + + Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> + +diff --git a/src/intel_module.c b/src/intel_module.c +index 1e402f0..8b3b196 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -192,34 +192,34 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_SDV_E_GT3, "Haswell SDV (GT3)" }, + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_D_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" }, + {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_M_GT3, "Haswell ULT Mobile (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_M_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_S_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" }, + {PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_B_GT3, "Haswell ULT (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_B_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" }, + {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_E_GT3, "Haswell ULT (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, + {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_D_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" }, + {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_M_GT3, "Haswell CRW Mobile (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_M_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_S_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_B_GT1, "Haswell CRW (GT1)" }, + {PCI_CHIP_HASWELL_CRW_B_GT2, "Haswell CRW (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_B_GT3, "Haswell CRW (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_B_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_E_GT1, "Haswell CRW (GT1)" }, + {PCI_CHIP_HASWELL_CRW_E_GT2, "Haswell CRW (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_E_GT3, "Haswell CRW (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_E_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, + {-1, NULL} + }; diff --git a/debian/patches/add-more-correct-hsw-names.diff b/debian/patches/add-more-correct-hsw-names.diff new file mode 100644 index 0000000..acc08ec --- /dev/null +++ b/debian/patches/add-more-correct-hsw-names.diff @@ -0,0 +1,73 @@ +commit 45c09bfe58c37bbf7965af25bdd4fa5c37c0908f +Author: Rodrigo Vivi <rodrigo.v...@gmail.com> +Date: Wed Jun 5 13:07:13 2013 -0300 + + Add more correct names for Haswell. + + As we find out more of the final product names for Haswell chipsets, we + need to update the user visible identification strings. + + Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com> + +diff --git a/src/intel_module.c b/src/intel_module.c +index 8b3b196..c1d0e09 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -160,19 +160,19 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" }, + {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" }, + {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" }, +- {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" }, +- {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" }, ++ {PCI_CHIP_HASWELL_D_GT1, "HD Graphics" }, ++ {PCI_CHIP_HASWELL_D_GT2, "HD Graphics 4600" }, + {PCI_CHIP_HASWELL_D_GT3, "Haswell Desktop (GT3)" }, +- {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" }, +- {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" }, ++ {PCI_CHIP_HASWELL_M_GT1, "HD Graphics" }, ++ {PCI_CHIP_HASWELL_M_GT2, "HD Graphics 4600" }, + {PCI_CHIP_HASWELL_M_GT3, "Haswell Mobile (GT3)" }, +- {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" }, +- {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" }, ++ {PCI_CHIP_HASWELL_S_GT1, "HD Graphics" }, ++ {PCI_CHIP_HASWELL_S_GT2, "HD Graphics P4600/P4700" }, + {PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" }, + {PCI_CHIP_HASWELL_B_GT1, "Haswell (GT1)" }, + {PCI_CHIP_HASWELL_B_GT2, "Haswell (GT2)" }, + {PCI_CHIP_HASWELL_B_GT3, "Haswell (GT3)" }, +- {PCI_CHIP_HASWELL_E_GT1, "Haswell (GT1)" }, ++ {PCI_CHIP_HASWELL_E_GT1, "HD Graphics" }, + {PCI_CHIP_HASWELL_E_GT2, "Haswell (GT2)" }, + {PCI_CHIP_HASWELL_E_GT3, "Haswell (GT3)" }, + {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" }, +@@ -193,23 +193,23 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, + {PCI_CHIP_HASWELL_ULT_D_GT3, "Iris(TM) Graphics 5100" }, +- {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" }, +- {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_M_GT3, "Iris(TM) Graphics 5100" }, ++ {PCI_CHIP_HASWELL_ULT_M_GT1, "HD Graphics" }, ++ {PCI_CHIP_HASWELL_ULT_M_GT2, "HD Graphics 4400" }, ++ {PCI_CHIP_HASWELL_ULT_M_GT3, "HD Graphics 5000" }, + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, + {PCI_CHIP_HASWELL_ULT_S_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" }, + {PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" }, + {PCI_CHIP_HASWELL_ULT_B_GT3, "Iris(TM) Graphics 5100" }, +- {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" }, +- {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT1, "HD Graphics" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT2, "HD Graphics 4200" }, + {PCI_CHIP_HASWELL_ULT_E_GT3, "Iris(TM) Graphics 5100" }, + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, +- {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, ++ {PCI_CHIP_HASWELL_CRW_D_GT2, "HD Graphics 4600" }, + {PCI_CHIP_HASWELL_CRW_D_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" }, +- {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" }, ++ {PCI_CHIP_HASWELL_CRW_M_GT2, "HD Graphics 4600" }, + {PCI_CHIP_HASWELL_CRW_M_GT3, "Iris(TM) Pro Graphics 5200" }, + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, diff --git a/debian/patches/add-more-reserved-hsw-ids.diff b/debian/patches/add-more-reserved-hsw-ids.diff new file mode 100644 index 0000000..60c489c --- /dev/null +++ b/debian/patches/add-more-reserved-hsw-ids.diff @@ -0,0 +1,204 @@ +commit 3ee42de066e4629f78e254c27d07dc33e16dbc02 +Author: Rodrigo Vivi <rodrigo.v...@gmail.com> +Date: Mon May 13 17:56:30 2013 -0300 + + Adding more reserved PCI IDs for Haswell. + + As Chris mentioned there is a tendency for us to find out more + PCI IDs only when users report. So let's add all new reserved Haswell IDs. + I didn't have better names for this reserved ids and didn't want to use rsvd1 + and rsvd2 groups, so I decided to use "B" and "E" that stands for the last + id digit. + + Cc: Chris Wilson <ch...@chris-wilson.co.uk> + Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com> + +diff --git a/src/intel_driver.h b/src/intel_driver.h +index 4b05e25..32f623b 100644 +--- a/src/intel_driver.h ++++ b/src/intel_driver.h +@@ -201,9 +201,12 @@ + #define PCI_CHIP_HASWELL_S_GT1 0x040A + #define PCI_CHIP_HASWELL_S_GT2 0x041A + #define PCI_CHIP_HASWELL_S_GT3 0x042A +-#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E +-#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E +-#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E ++#define PCI_CHIP_HASWELL_B_GT1 0x040B ++#define PCI_CHIP_HASWELL_B_GT2 0x041B ++#define PCI_CHIP_HASWELL_B_GT3 0x042B ++#define PCI_CHIP_HASWELL_E_GT1 0x040E ++#define PCI_CHIP_HASWELL_E_GT2 0x041E ++#define PCI_CHIP_HASWELL_E_GT3 0x042E + + #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 + #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 +@@ -214,9 +217,12 @@ + #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A + #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A + #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A +-#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E +-#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E +-#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E ++#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0E ++#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1E ++#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2E ++#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E ++#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E ++#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E + + #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 + #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 +@@ -227,9 +233,12 @@ + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A + #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A +-#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E +-#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E +-#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E ++#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B ++#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B ++#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B ++#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E ++#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E ++#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E + + #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 + #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 +@@ -240,9 +249,12 @@ + #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A + #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A + #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A +-#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E +-#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E +-#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E ++#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B ++#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B ++#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B ++#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E ++#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E ++#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E + + #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 + #define PCI_CHIP_VALLEYVIEW_1 0x0f31 +diff --git a/src/intel_module.c b/src/intel_module.c +index 6439eea..1e402f0 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -169,6 +169,12 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" }, + {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" }, + {PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" }, ++ {PCI_CHIP_HASWELL_B_GT1, "Haswell (GT1)" }, ++ {PCI_CHIP_HASWELL_B_GT2, "Haswell (GT2)" }, ++ {PCI_CHIP_HASWELL_B_GT3, "Haswell (GT3)" }, ++ {PCI_CHIP_HASWELL_E_GT1, "Haswell (GT1)" }, ++ {PCI_CHIP_HASWELL_E_GT2, "Haswell (GT2)" }, ++ {PCI_CHIP_HASWELL_E_GT3, "Haswell (GT3)" }, + {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" }, + {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" }, + {PCI_CHIP_HASWELL_SDV_D_GT3, "Haswell SDV Desktop (GT3)" }, +@@ -178,6 +184,12 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" }, + {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" }, + {PCI_CHIP_HASWELL_SDV_S_GT3, "Haswell SDV Server (GT3)" }, ++ {PCI_CHIP_HASWELL_SDV_B_GT1, "Haswell SDV (GT1)" }, ++ {PCI_CHIP_HASWELL_SDV_B_GT2, "Haswell SDV (GT2)" }, ++ {PCI_CHIP_HASWELL_SDV_B_GT3, "Haswell SDV (GT3)" }, ++ {PCI_CHIP_HASWELL_SDV_E_GT1, "Haswell SDV (GT1)" }, ++ {PCI_CHIP_HASWELL_SDV_E_GT2, "Haswell SDV (GT2)" }, ++ {PCI_CHIP_HASWELL_SDV_E_GT3, "Haswell SDV (GT3)" }, + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, + {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" }, +@@ -187,6 +199,12 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, + {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" }, ++ {PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" }, ++ {PCI_CHIP_HASWELL_ULT_B_GT3, "Haswell ULT (GT3)" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" }, ++ {PCI_CHIP_HASWELL_ULT_E_GT3, "Haswell ULT (GT3)" }, + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, + {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, + {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" }, +@@ -196,6 +214,12 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, + {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_B_GT1, "Haswell CRW (GT1)" }, ++ {PCI_CHIP_HASWELL_CRW_B_GT2, "Haswell CRW (GT2)" }, ++ {PCI_CHIP_HASWELL_CRW_B_GT3, "Haswell CRW (GT3)" }, ++ {PCI_CHIP_HASWELL_CRW_E_GT1, "Haswell CRW (GT1)" }, ++ {PCI_CHIP_HASWELL_CRW_E_GT2, "Haswell CRW (GT2)" }, ++ {PCI_CHIP_HASWELL_CRW_E_GT3, "Haswell CRW (GT3)" }, + {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, + {-1, NULL} + }; +@@ -277,9 +301,12 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT3_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT3, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT3, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), +@@ -290,9 +317,12 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT3_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT3, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT3, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), +@@ -303,9 +333,13 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT3_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT3, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT3, &intel_haswell_info ), ++ + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ), +@@ -315,9 +349,12 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT3_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT3, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT1, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT2, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT3, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), diff --git a/debian/patches/add-reserved-hsw-ids.diff b/debian/patches/add-reserved-hsw-ids.diff new file mode 100644 index 0000000..469763d --- /dev/null +++ b/debian/patches/add-reserved-hsw-ids.diff @@ -0,0 +1,107 @@ +commit ab576a42650d8a743dd91108f774c220d866de95 +Author: Chris Wilson <ch...@chris-wilson.co.uk> +Date: Sat Apr 27 12:06:30 2013 +0100 + + Add all reserved PCI-IDs for Haswell + + There is a tendency for a product to ship based on a 'reserved' PCI-ID + prior to us being notified about it. In other words, the first we find + out about such a product is when customers start complaining about their + shiny new hardware not being supported... + + References: https://bugs.freedesktop.org/show_bug.cgi?id=63701 + Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> + +diff --git a/src/intel_driver.h b/src/intel_driver.h +index 0dda5b1..d109c7e 100644 +--- a/src/intel_driver.h ++++ b/src/intel_driver.h +@@ -201,6 +201,10 @@ + #define PCI_CHIP_HASWELL_S_GT1 0x040A + #define PCI_CHIP_HASWELL_S_GT2 0x041A + #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A ++#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E ++#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E ++#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E ++ + #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 + #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 + #define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 +@@ -210,6 +214,10 @@ + #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A + #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A + #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A ++#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E ++#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E ++#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E ++ + #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 + #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 + #define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 +@@ -219,6 +227,10 @@ + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A + #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A ++#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E ++#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E ++#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E ++ + #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 + #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 + #define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 +@@ -228,6 +240,9 @@ + #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A + #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A + #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A ++#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E ++#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E ++#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E + + #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 + #define PCI_CHIP_VALLEYVIEW_1 0x0f31 +diff --git a/src/intel_module.c b/src/intel_module.c +index 4434ed0..73cfa97 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -277,6 +277,10 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ), ++ + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), +@@ -286,6 +290,10 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ), ++ + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), +@@ -295,6 +303,9 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), +@@ -304,6 +315,9 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), diff --git a/debian/patches/add-vlv-ids.diff b/debian/patches/add-vlv-ids.diff new file mode 100644 index 0000000..83e8b54 --- /dev/null +++ b/debian/patches/add-vlv-ids.diff @@ -0,0 +1,36 @@ +commit 4c45e3fe456d211afc6ba69878b413a72ef5d0bf +Author: Chris Wilson <ch...@chris-wilson.co.uk> +Date: Tue Feb 5 14:45:39 2013 +0000 + + intel: add more ValleyView PCI IDs + + Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> + +diff --git a/src/intel_driver.h b/src/intel_driver.h +index b77b8d1..c98025b 100644 +--- a/src/intel_driver.h ++++ b/src/intel_driver.h +@@ -230,6 +230,9 @@ + #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A + + #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 ++#define PCI_CHIP_VALLEYVIEW_1 0x0f31 ++#define PCI_CHIP_VALLEYVIEW_2 0x0f32 ++#define PCI_CHIP_VALLEYVIEW_3 0x0f33 + + #endif + +diff --git a/src/intel_module.c b/src/intel_module.c +index e15dd90..8f681c9 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -306,6 +306,9 @@ static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), + + INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), + #endif diff --git a/debian/patches/fix-hsw-crw-ids.diff b/debian/patches/fix-hsw-crw-ids.diff new file mode 100644 index 0000000..45e33e0 --- /dev/null +++ b/debian/patches/fix-hsw-crw-ids.diff @@ -0,0 +1,40 @@ +commit ae3531c3a1d72a73b25c5563b4db029f051262cb +Author: Chris Wilson <ch...@chris-wilson.co.uk> +Date: Fri Mar 1 23:46:07 2013 +0000 + + Fix Haswell CRW PCI-IDs + + As we missed the PCI-ID for the CRW GT1 variant, we would not have enabled + render support for those particular Haswell machines. + + Reported-by: Kenneth Graunke <kenn...@whitecape.org> + +diff --git a/src/intel_driver.h b/src/intel_driver.h +index c98025b..0dda5b1 100644 +--- a/src/intel_driver.h ++++ b/src/intel_driver.h +@@ -219,15 +219,15 @@ + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A + #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +-#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12 +-#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22 +-#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32 +-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 +-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A +-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A ++#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 ++#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 ++#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 ++#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 ++#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 ++#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 ++#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A ++#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A ++#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A + + #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 + #define PCI_CHIP_VALLEYVIEW_1 0x0f31 diff --git a/debian/patches/fix-hsw-gt3-names.diff b/debian/patches/fix-hsw-gt3-names.diff new file mode 100644 index 0000000..c6d600c --- /dev/null +++ b/debian/patches/fix-hsw-gt3-names.diff @@ -0,0 +1,217 @@ +commit ee96de8b1e7e4a305ee31c0ece1d9d38df8328f9 +Author: Rodrigo Vivi <rodrigo.v...@gmail.com> +Date: Mon May 13 17:56:29 2013 -0300 + + Fix Haswell GT3 names. + + When publishing first HSW ids we weren't allowed to use "GT3" codname. + But this is the correct codname and Mesa is using it already. + So to avoid people getting confused why in Mesa it is called GT3 and here + it is called GT2_PLUS let's fix this name in a standard and correct way. + + Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com> + +diff --git a/src/intel_driver.h b/src/intel_driver.h +index d109c7e..4b05e25 100644 +--- a/src/intel_driver.h ++++ b/src/intel_driver.h +@@ -194,55 +194,55 @@ + + #define PCI_CHIP_HASWELL_D_GT1 0x0402 + #define PCI_CHIP_HASWELL_D_GT2 0x0412 +-#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422 ++#define PCI_CHIP_HASWELL_D_GT3 0x0422 + #define PCI_CHIP_HASWELL_M_GT1 0x0406 + #define PCI_CHIP_HASWELL_M_GT2 0x0416 +-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 ++#define PCI_CHIP_HASWELL_M_GT3 0x0426 + #define PCI_CHIP_HASWELL_S_GT1 0x040A + #define PCI_CHIP_HASWELL_S_GT2 0x041A +-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A ++#define PCI_CHIP_HASWELL_S_GT3 0x042A + #define PCI_CHIP_HASWELL_GT1_RSVD 0x040E + #define PCI_CHIP_HASWELL_GT2_RSVD 0x041E +-#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E ++#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E + + #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 + #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 +-#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 ++#define PCI_CHIP_HASWELL_SDV_D_GT3 0x0C22 + #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 + #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 ++#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 + #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A + #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A ++#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A + #define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E + #define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E +-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E ++#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E + + #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 + #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 +-#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 ++#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22 + #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 + #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 ++#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A ++#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A + #define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E + #define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E +-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E ++#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E + + #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 + #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 +-#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 ++#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22 + #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 + #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 ++#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 + #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A + #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A ++#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A + #define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E + #define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E +-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E ++#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E + + #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 + #define PCI_CHIP_VALLEYVIEW_1 0x0f31 +diff --git a/src/intel_module.c b/src/intel_module.c +index 73cfa97..6439eea 100644 +--- a/src/intel_module.c ++++ b/src/intel_module.c +@@ -162,40 +162,40 @@ static const SymTabRec intel_chipsets[] = { + {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" }, + {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" }, + {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" }, ++ {PCI_CHIP_HASWELL_D_GT3, "Haswell Desktop (GT3)" }, + {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" }, + {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" }, ++ {PCI_CHIP_HASWELL_M_GT3, "Haswell Mobile (GT3)" }, + {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" }, + {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" }, +- {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" }, ++ {PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" }, + {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" }, + {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" }, ++ {PCI_CHIP_HASWELL_SDV_D_GT3, "Haswell SDV Desktop (GT3)" }, + {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" }, + {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" }, ++ {PCI_CHIP_HASWELL_SDV_M_GT3, "Haswell SDV Mobile (GT3)" }, + {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" }, + {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" }, +- {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" }, ++ {PCI_CHIP_HASWELL_SDV_S_GT3, "Haswell SDV Server (GT3)" }, + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" }, ++ {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" }, + {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" }, + {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" }, ++ {PCI_CHIP_HASWELL_ULT_M_GT3, "Haswell ULT Mobile (GT3)" }, + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, +- {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" }, ++ {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" }, + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, + {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" }, ++ {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" }, + {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" }, + {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" }, ++ {PCI_CHIP_HASWELL_CRW_M_GT3, "Haswell CRW Mobile (GT3)" }, + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, +- {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" }, ++ {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" }, + {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, + {-1, NULL} + }; +@@ -270,54 +270,54 @@ static const struct pci_id_match intel_device_match[] = { + + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT3_RSVD, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT3_RSVD, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT3_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ), +- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ), ++ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT3_RSVD, &intel_haswell_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), diff --git a/debian/patches/series b/debian/patches/series index b5a308d..b481396 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1 +1,8 @@ fix-glamor-check.diff +add-vlv-ids.diff +fix-hsw-crw-ids.diff +add-reserved-hsw-ids.diff +fix-hsw-gt3-names.diff +add-more-reserved-hsw-ids.diff +add-known-hsw-names.diff +add-more-correct-hsw-names.diff -- To UNSUBSCRIBE, email to debian-x-requ...@lists.debian.org with a subject of "unsubscribe". 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