Makefile.am | 12 +--
VERSION | 2
debian/changelog | 4 -
debian/control | 2
include/pci_ids/radeonsi_pci_ids.h | 7 ++
src/gallium/auxiliary/vl/vl_compositor.c | 2
src/gallium/drivers/radeon/radeon_video.c | 7 +-
src/gallium/state_trackers/vdpau/device.c | 43 +++++++++++++-
src/gallium/state_trackers/vdpau/output.c | 42 +++++++++----
src/gallium/state_trackers/vdpau/vdpau_private.h | 1
src/glsl/glcpp/glcpp-lex.l | 10 ++-
src/mesa/Makefile.am | 3
src/mesa/drivers/dri/i965/brw_eu_compact.c | 14 +---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 1
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 7 ++
src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp | 5 -
16 files changed, 119 insertions(+), 43 deletions(-)
New commits:
commit 2e5e3d22fc2a8d875ca1f8d311a409ba60a21b56
Author: Maarten Lankhorst <maarten.lankho...@canonical.com>
Date: Thu Aug 14 15:02:57 2014 +0200
Remove mention of tdfx.
Conflicts:
debian/changelog
debian/control
diff --git a/debian/changelog b/debian/changelog
index c5d7c4e..ae0bbb8 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -3,6 +3,7 @@ mesa (10.3~rc2-1) UNRELEASED; urgency=low
[ Maarten Lankhorst ]
* Build with llvm 3.5.
* New upstream release.
+ * Remove mention of tdfx.
[ Timo Aaltonen ]
* mesa-common-dev: Add glcorearb.h.
diff --git a/debian/control b/debian/control
index 0c8a94b..e646957 100644
--- a/debian/control
+++ b/debian/control
@@ -676,8 +676,6 @@ Description: free implementation of the OpenGL API -- DRI
modules
.
For a complete description of Mesa, please look at the
libgl1-mesa-swx11 package.
- .
- The tdfx DRI module needs libglide3 to enable direct rendering.
Package: libgl1-mesa-dri-dbg
Section: debug
commit d5fb28e13755988ac87a5910103d9b883f360cd7
Author: Maarten Lankhorst <maarten.lankho...@canonical.com>
Date: Mon Sep 1 11:26:10 2014 +0200
bump changelog
diff --git a/debian/changelog b/debian/changelog
index 79c6177..c5d7c4e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,7 +1,8 @@
-mesa (10.3~rc1-1) UNRELEASED; urgency=low
+mesa (10.3~rc2-1) UNRELEASED; urgency=low
[ Maarten Lankhorst ]
* Build with llvm 3.5.
+ * New upstream release.
[ Timo Aaltonen ]
* mesa-common-dev: Add glcorearb.h.
commit 390a9f6cb7ddc755380a680ff8e07b308e5b31b4
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Sun Aug 31 19:29:42 2014 +0100
Increment version to 10.3.0-rc2
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
diff --git a/VERSION b/VERSION
index 9cad0c5..87d81b2 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.3.0-rc1
+10.3.0-rc2
commit 0fbb9a599df898d4e1166d6d6f00cb34a0524bea
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Sun Aug 31 23:16:15 2014 +0100
mesa: fix make tarballs
Current method of generating distribution tar-balls involves manually
invoking make + target name in the appropriate places. This temporary
solution is used until we get 'make dist' working.
Currently it does not work, as in order to have the target (which is
also a filename) available in the final Makefile we need to add a PHONY
target + use the correct target name.
Cc: "10.2 10.3" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
(cherry picked from commit 88cbe3908f0ea08228a5ffb1808f98b6906c4416)
diff --git a/Makefile.am b/Makefile.am
index d2916da..111c1c8 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -64,7 +64,7 @@ IGNORE_FILES = \
parsers: configure
$(MAKE) -C src/glsl glsl_parser.cpp glsl_parser.h glsl_lexer.cpp
glcpp/glcpp-lex.c glcpp/glcpp-parse.c glcpp/glcpp-parse.h
- $(MAKE) -C src/mesa program/lex.yy.c program/program_parse.tab.c
program/program_parse.tab.h
+ $(MAKE) -C src/mesa ../../src/mesa/program/lex.yy.c
../../src/mesa/program/program_parse.tab.c
../../src/mesa/program/program_parse.tab.h
# Everything for new a Mesa release:
ARCHIVES = $(PACKAGE_NAME).tar.gz \
diff --git a/src/mesa/Makefile.am b/src/mesa/Makefile.am
index e71bccb..b23208a 100644
--- a/src/mesa/Makefile.am
+++ b/src/mesa/Makefile.am
@@ -36,7 +36,8 @@ endif
gldir = $(includedir)/GL
gl_HEADERS = $(top_srcdir)/include/GL/*.h
-.PHONY: $(BUILDDIR)main/git_sha1.h.tmp
+.PHONY: $(BUILDDIR)main/git_sha1.h.tmp $(BUILDDIR)program/lex.yy.c
$(BUILDDIR)program/program_parse.tab.c $(BUILDDIR)program/program_parse.tab.h
+
$(BUILDDIR)main/git_sha1.h.tmp:
@touch main/git_sha1.h.tmp
@if test -d $(top_srcdir)/.git; then \
commit 2310a4b4cf0fd7a4cd04dd9aba5c89f52070e5d2
Author: Matt Turner <matts...@gmail.com>
Date: Thu Aug 28 20:16:42 2014 -0700
i965/vec4: Update register coalescing test.
In commit 04895f5c I added support for reswizzling writemasks. This test
was checking that we didn't support this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82881
(cherry picked from commit 8b5ac1df17608e0d0d5ce412988ee8de97f61405)
diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
index 149174c..16e6270 100644
--- a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
@@ -241,8 +241,5 @@ TEST_F(register_coalesce_test, test_channel_mul_grf)
register_coalesce(v);
- /* This path isn't supported yet in the reswizzling code, so we're checking
- * that we haven't done anything bad to scalar non-DP[234]s.
- */
- EXPECT_NE(mul->dst.reg, to.reg);
+ EXPECT_EQ(mul->dst.reg, to.reg);
}
commit 8ef3d4fe03de1b370e255a3c900719a8cce59599
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Fri Aug 29 15:15:43 2014 -0700
i965: Add 2x MSAA support to Broadwell fast clear code.
According to the cited documentation section (but in the newer docs),
x_scaledown is the same for 2x and 4x MSAA.
+47 piglits.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83081
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Matt Turner <matts...@gmail.com>
Cc: "10.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit e34a363a781a24b2cf6930c4d37f781ffec8a19a)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 4fb20d7..aa3a60d 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -282,6 +282,7 @@ get_fast_clear_rect(struct brw_context *brw, struct
gl_framebuffer *fb,
* factor is 2 vertically and either 2 or 8 horizontally.
*/
switch (irb->mt->num_samples) {
+ case 2:
case 4:
x_scaledown = 8;
break;
commit 0c67167370bfbfee7d456812c13a87b239530dc9
Author: Christian König <christian.koe...@amd.com>
Date: Sun Aug 24 12:22:08 2014 +0200
radeon/uvd: fix field handling on R6XX style UVD
The first UVD generation can only do frame based output.
Signed-off-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit 80771e47b6c1e47ab55f17311e1d4e227a9eb3d8)
Nominated-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/gallium/drivers/radeon/radeon_video.c
b/src/gallium/drivers/radeon/radeon_video.c
index 17e9a59..6dcee45 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -251,8 +251,11 @@ int rvid_get_video_param(struct pipe_screen *screen,
profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- /* and MPEG2 only with shaders */
- return codec != PIPE_VIDEO_FORMAT_MPEG12;
+ /* MPEG2 only with shaders and no support for
+ interlacing on R6xx style UVD */
+ return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
+ /* TODO: RV770 might actually work */
+ rscreen->family > CHIP_RV770;
default:
break;
}
commit 60f136eed9eb6d0622e44f6634162a702ba57c02
Author: Christian König <christian.koe...@amd.com>
Date: Wed Aug 13 21:01:33 2014 +0200
vl/compositor: set the scissor before clearing the render target
Otherwise we clear areas that shouldn't be cleared.
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 03a99ba9e41ea86355a4febbe0b1a114d5455b9f)
diff --git a/src/gallium/auxiliary/vl/vl_compositor.c
b/src/gallium/auxiliary/vl/vl_compositor.c
index 839fd27..6bd1a88 100644
--- a/src/gallium/auxiliary/vl/vl_compositor.c
+++ b/src/gallium/auxiliary/vl/vl_compositor.c
@@ -1060,6 +1060,7 @@ vl_compositor_render(struct vl_compositor_state *s,
s->scissor.maxx = dst_surface->width;
s->scissor.maxy = dst_surface->height;
}
+ c->pipe->set_scissor_states(c->pipe, 0, 1, &s->scissor);
gen_vertex_data(c, s, dirty_area);
@@ -1072,7 +1073,6 @@ vl_compositor_render(struct vl_compositor_state *s,
dirty_area->x1 = dirty_area->y1 = MIN_DIRTY;
}
- c->pipe->set_scissor_states(c->pipe, 0, 1, &s->scissor);
c->pipe->set_framebuffer_state(c->pipe, &c->fb_state);
c->pipe->bind_vs_state(c->pipe, c->vs);
c->pipe->set_vertex_buffers(c->pipe, 0, 1, &c->vertex_buf);
commit d2fb1da46d1bf9f5f05175a0ed30919fc0c118bd
Author: Christian König <christian.koe...@amd.com>
Date: Wed Aug 13 20:21:06 2014 +0200
st/vdpau: fix vlVdpOutputSurfaceRender(Output|Bitmap)Surface
Correctly handle that the source_surface is only optional.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80561
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit b73c20759fe1b4a96296bed58637f5ded7c9155c)
diff --git a/src/gallium/state_trackers/vdpau/device.c
b/src/gallium/state_trackers/vdpau/device.c
index 9c5ec60..efc1fde 100644
--- a/src/gallium/state_trackers/vdpau/device.c
+++ b/src/gallium/state_trackers/vdpau/device.c
@@ -42,6 +42,8 @@ vdp_imp_device_create_x11(Display *display, int screen,
VdpDevice *device,
VdpGetProcAddress **get_proc_address)
{
struct pipe_screen *pscreen;
+ struct pipe_resource *res, res_tmpl;
+ struct pipe_sampler_view sv_tmpl;
vlVdpDevice *dev = NULL;
VdpStatus ret;
@@ -79,6 +81,43 @@ vdp_imp_device_create_x11(Display *display, int screen,
VdpDevice *device,
goto no_context;
}
+ memset(&res_tmpl, 0, sizeof(res_tmpl));
+
+ res_tmpl.target = PIPE_TEXTURE_2D;
+ res_tmpl.format = PIPE_FORMAT_R8G8B8A8_UNORM;
+ res_tmpl.width0 = 1;
+ res_tmpl.height0 = 1;
+ res_tmpl.depth0 = 1;
+ res_tmpl.array_size = 1;
+ res_tmpl.bind = PIPE_BIND_SAMPLER_VIEW;
+ res_tmpl.usage = PIPE_USAGE_DEFAULT;
+
+ if (!CheckSurfaceParams(pscreen, &res_tmpl)) {
+ ret = VDP_STATUS_NO_IMPLEMENTATION;
+ goto no_resource;
+ }
+
+ res = pscreen->resource_create(pscreen, &res_tmpl);
+ if (!res) {
+ ret = VDP_STATUS_RESOURCES;
+ goto no_resource;
+ }
+
+ memset(&sv_tmpl, 0, sizeof(sv_tmpl));
+ u_sampler_view_default_template(&sv_tmpl, res, res->format);
+
+ sv_tmpl.swizzle_r = PIPE_SWIZZLE_ONE;
+ sv_tmpl.swizzle_g = PIPE_SWIZZLE_ONE;
+ sv_tmpl.swizzle_b = PIPE_SWIZZLE_ONE;
+ sv_tmpl.swizzle_a = PIPE_SWIZZLE_ONE;
+
+ dev->dummy_sv = dev->context->create_sampler_view(dev->context, res,
&sv_tmpl);
+ pipe_resource_reference(&res, NULL);
+ if (!dev->dummy_sv) {
+ ret = VDP_STATUS_RESOURCES;
+ goto no_resource;
+ }
+
*device = vlAddDataHTAB(dev);
if (*device == 0) {
ret = VDP_STATUS_ERROR;
@@ -93,8 +132,9 @@ vdp_imp_device_create_x11(Display *display, int screen,
VdpDevice *device,
return VDP_STATUS_OK;
no_handle:
+ pipe_sampler_view_reference(&dev->dummy_sv, NULL);
+no_resource:
dev->context->destroy(dev->context);
- /* Destroy vscreen */
no_context:
vl_screen_destroy(dev->vscreen);
no_vscreen:
@@ -185,6 +225,7 @@ vlVdpDeviceFree(vlVdpDevice *dev)
{
pipe_mutex_destroy(dev->mutex);
vl_compositor_cleanup(&dev->compositor);
+ pipe_sampler_view_reference(&dev->dummy_sv, NULL);
dev->context->destroy(dev->context);
vl_screen_destroy(dev->vscreen);
FREE(dev);
diff --git a/src/gallium/state_trackers/vdpau/output.c
b/src/gallium/state_trackers/vdpau/output.c
index caae50f..3248f76 100644
--- a/src/gallium/state_trackers/vdpau/output.c
+++ b/src/gallium/state_trackers/vdpau/output.c
@@ -624,9 +624,9 @@ vlVdpOutputSurfaceRenderOutputSurface(VdpOutputSurface
destination_surface,
uint32_t flags)
{
vlVdpOutputSurface *dst_vlsurface;
- vlVdpOutputSurface *src_vlsurface;
struct pipe_context *context;
+ struct pipe_sampler_view *src_sv;
struct vl_compositor *compositor;
struct vl_compositor_state *cstate;
@@ -639,12 +639,19 @@ vlVdpOutputSurfaceRenderOutputSurface(VdpOutputSurface
destination_surface,
if (!dst_vlsurface)
return VDP_STATUS_INVALID_HANDLE;
- src_vlsurface = vlGetDataHTAB(source_surface);
- if (!src_vlsurface)
- return VDP_STATUS_INVALID_HANDLE;
+ if (source_surface == VDP_INVALID_HANDLE) {
+ src_sv = dst_vlsurface->device->dummy_sv;
+
+ } else {
+ vlVdpOutputSurface *src_vlsurface = vlGetDataHTAB(source_surface);
+ if (!src_vlsurface)
+ return VDP_STATUS_INVALID_HANDLE;
- if (dst_vlsurface->device != src_vlsurface->device)
- return VDP_STATUS_HANDLE_DEVICE_MISMATCH;
+ if (dst_vlsurface->device != src_vlsurface->device)
+ return VDP_STATUS_HANDLE_DEVICE_MISMATCH;
+
+ src_sv = src_vlsurface->sampler_view;
+ }
pipe_mutex_lock(dst_vlsurface->device->mutex);
vlVdpResolveDelayedRendering(dst_vlsurface->device, NULL, NULL);
@@ -657,7 +664,7 @@ vlVdpOutputSurfaceRenderOutputSurface(VdpOutputSurface
destination_surface,
vl_compositor_clear_layers(cstate);
vl_compositor_set_layer_blend(cstate, 0, blend, false);
- vl_compositor_set_rgba_layer(cstate, compositor, 0,
src_vlsurface->sampler_view,
+ vl_compositor_set_rgba_layer(cstate, compositor, 0, src_sv,
RectToPipe(source_rect, &src_rect), NULL,
ColorsToPipe(colors, flags, vlcolors));
STATIC_ASSERT(VL_COMPOSITOR_ROTATE_0 == VDP_OUTPUT_SURFACE_RENDER_ROTATE_0);
@@ -688,9 +695,9 @@ vlVdpOutputSurfaceRenderBitmapSurface(VdpOutputSurface
destination_surface,
uint32_t flags)
{
vlVdpOutputSurface *dst_vlsurface;
- vlVdpBitmapSurface *src_vlsurface;
struct pipe_context *context;
+ struct pipe_sampler_view *src_sv;
struct vl_compositor *compositor;
struct vl_compositor_state *cstate;
@@ -703,12 +710,19 @@ vlVdpOutputSurfaceRenderBitmapSurface(VdpOutputSurface
destination_surface,
if (!dst_vlsurface)
return VDP_STATUS_INVALID_HANDLE;
- src_vlsurface = vlGetDataHTAB(source_surface);
- if (!src_vlsurface)
- return VDP_STATUS_INVALID_HANDLE;
+ if (source_surface == VDP_INVALID_HANDLE) {
+ src_sv = dst_vlsurface->device->dummy_sv;
+
+ } else {
+ vlVdpBitmapSurface *src_vlsurface = vlGetDataHTAB(source_surface);
+ if (!src_vlsurface)
+ return VDP_STATUS_INVALID_HANDLE;
- if (dst_vlsurface->device != src_vlsurface->device)
- return VDP_STATUS_HANDLE_DEVICE_MISMATCH;
+ if (dst_vlsurface->device != src_vlsurface->device)
+ return VDP_STATUS_HANDLE_DEVICE_MISMATCH;
+
+ src_sv = src_vlsurface->sampler_view;
+ }
context = dst_vlsurface->device->context;
compositor = &dst_vlsurface->device->compositor;
@@ -721,7 +735,7 @@ vlVdpOutputSurfaceRenderBitmapSurface(VdpOutputSurface
destination_surface,
vl_compositor_clear_layers(cstate);
vl_compositor_set_layer_blend(cstate, 0, blend, false);
- vl_compositor_set_rgba_layer(cstate, compositor, 0,
src_vlsurface->sampler_view,
+ vl_compositor_set_rgba_layer(cstate, compositor, 0, src_sv,
RectToPipe(source_rect, &src_rect), NULL,
ColorsToPipe(colors, flags, vlcolors));
vl_compositor_set_layer_rotation(cstate, 0, flags & 3);
diff --git a/src/gallium/state_trackers/vdpau/vdpau_private.h
b/src/gallium/state_trackers/vdpau/vdpau_private.h
index 65f8e47..d1443a0 100644
--- a/src/gallium/state_trackers/vdpau/vdpau_private.h
+++ b/src/gallium/state_trackers/vdpau/vdpau_private.h
@@ -348,6 +348,7 @@ typedef struct
struct vl_screen *vscreen;
struct pipe_context *context;
struct vl_compositor compositor;
+ struct pipe_sampler_view *dummy_sv;
pipe_mutex mutex;
struct {
commit 627d31dc36be6a92775b038bc4a26a96df8e7191
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Aug 18 11:36:12 2014 -0700
glcpp: Don't use alternation in the lookahead for empty pragmas.
We've found that there's a buffer overrun bug in flex that's triggered by
using alternation in a lookahead pattern.
Fortunately, we don't need to match the exact {NEWLINE} expression to
detect an empty pragma. It suffices to verify that there are no non-space
characters before any newline character. So we can use a simple [\r\n] to
get the desired behavior while avoiding the flex bug.
Fixes the regression of piglit's 17000-consecutive-chars-identifier test,
(which has been crashing since commit
04e40fd337a244ee77ef9553985e9398ff0344af ).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82472
Signed-off-by: Carl Worth <cwo...@cworth.org>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
CC: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 23163df24cf96107ee8ccb372db20f49e9d88948)
diff --git a/src/glsl/glcpp/glcpp-lex.l b/src/glsl/glcpp/glcpp-lex.l
index 98d500e..fa9aa50 100644
--- a/src/glsl/glcpp/glcpp-lex.l
+++ b/src/glsl/glcpp/glcpp-lex.l
@@ -289,8 +289,14 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
}
/* Swallow empty #pragma directives, (to avoid confusing the
- * downstream compiler). */
-<HASH>pragma{HSPACE}*/{NEWLINE} {
+ * downstream compiler).
+ *
+ * Note: We use a simple regular expression for the lookahead
+ * here. Specifically, we cannot use the complete {NEWLINE} expression
+ * since it uses alternation and we've found that there's a flex bug
+ * where using alternation in the lookahead portion of a pattern
+ * triggers a buffer overrun. */
+<HASH>pragma{HSPACE}*/[\r\n] {
BEGIN INITIAL;
}
commit e4f54d8b470995b88afb0bbf247a8f0a908b0817
Author: Carl Worth <cwo...@cworth.org>
Date: Thu Aug 21 09:03:02 2014 -0700
Makefile: Switch from md5sums to sha256sums
We switched to these several stable releases ago, (since the MD5 algorithm
has
been broken for some time), but only now did I get around to fixing this in
the Makefile rather than just performing this step manually.
CC: "10.2 10.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 46d03d37bf3a75e86f9f8ab56c6a939d04f23383)
diff --git a/Makefile.am b/Makefile.am
index 4780510..d2916da 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -71,7 +71,7 @@ ARCHIVES = $(PACKAGE_NAME).tar.gz \
$(PACKAGE_NAME).tar.bz2 \
$(PACKAGE_NAME).zip
-tarballs: md5
+tarballs: checksums
rm -f ../$(PACKAGE_DIR) $(PACKAGE_NAME).tar
manifest.txt: .git
@@ -98,9 +98,9 @@ $(PACKAGE_NAME).zip: parsers ../$(PACKAGE_DIR) manifest.txt
zip -q -@ $(PACKAGE_NAME).zip < $(PACKAGE_DIR)/manifest.txt ; \
mv $(PACKAGE_NAME).zip $(PACKAGE_DIR)
-md5: $(ARCHIVES)
- @-md5sum $(PACKAGE_NAME).tar.gz
- @-md5sum $(PACKAGE_NAME).tar.bz2
- @-md5sum $(PACKAGE_NAME).zip
+checksums: $(ARCHIVES)
+ @-sha256sum $(PACKAGE_NAME).tar.gz
+ @-sha256sum $(PACKAGE_NAME).tar.bz2
+ @-sha256sum $(PACKAGE_NAME).zip
.PHONY: tarballs md5
commit 2edc941e75c26c93d0954f036d632fde799ed7f5
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Thu Aug 21 11:16:15 2014 -0400
radeonsi: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 153df688349dd6e55fa4c280ed6c8abd02c5f890)
diff --git a/include/pci_ids/radeonsi_pci_ids.h
b/include/pci_ids/radeonsi_pci_ids.h
index 6412f08..571e863 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -38,6 +38,7 @@ CHIPSET(0x6828, VERDE_6828, VERDE)
CHIPSET(0x6829, VERDE_6829, VERDE)
CHIPSET(0x682A, VERDE_682A, VERDE)
CHIPSET(0x682B, VERDE_682B, VERDE)
+CHIPSET(0x682C, VERDE_682C, VERDE)
CHIPSET(0x682D, VERDE_682D, VERDE)
CHIPSET(0x682F, VERDE_682F, VERDE)
CHIPSET(0x6830, VERDE_6830, VERDE)
@@ -54,8 +55,11 @@ CHIPSET(0x6600, OLAND_6600, OLAND)
CHIPSET(0x6601, OLAND_6601, OLAND)
CHIPSET(0x6602, OLAND_6602, OLAND)
CHIPSET(0x6603, OLAND_6603, OLAND)
+CHIPSET(0x6604, OLAND_6604, OLAND)
+CHIPSET(0x6605, OLAND_6605, OLAND)
CHIPSET(0x6606, OLAND_6606, OLAND)
CHIPSET(0x6607, OLAND_6607, OLAND)
+CHIPSET(0x6608, OLAND_6608, OLAND)
CHIPSET(0x6610, OLAND_6610, OLAND)
CHIPSET(0x6611, OLAND_6611, OLAND)
CHIPSET(0x6613, OLAND_6613, OLAND)
commit eb9681938687a8ba5bb9ec4c5456ff7d6c6794ec
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Thu Aug 21 11:13:17 2014 -0400
radeonsi: add new CIK pci ids
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit f50b6b489534f8f362953cbe08d37233f1eab669)
diff --git a/include/pci_ids/radeonsi_pci_ids.h
b/include/pci_ids/radeonsi_pci_ids.h
index 5099c74..6412f08 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -73,6 +73,8 @@ CHIPSET(0x666F, HAINAN_666F, HAINAN)
CHIPSET(0x6640, BONAIRE_6640, BONAIRE)
CHIPSET(0x6641, BONAIRE_6641, BONAIRE)
+CHIPSET(0x6646, BONAIRE_6646, BONAIRE)
+CHIPSET(0x6647, BONAIRE_6647, BONAIRE)
CHIPSET(0x6649, BONAIRE_6649, BONAIRE)
CHIPSET(0x6650, BONAIRE_6650, BONAIRE)
CHIPSET(0x6651, BONAIRE_6651, BONAIRE)
@@ -132,6 +134,7 @@ CHIPSET(0x1313, KAVERI_1313, KAVERI)
CHIPSET(0x1315, KAVERI_1315, KAVERI)
CHIPSET(0x1316, KAVERI_1316, KAVERI)
CHIPSET(0x1317, KAVERI_1317, KAVERI)
+CHIPSET(0x1318, KAVERI_1318, KAVERI)
CHIPSET(0x131B, KAVERI_131B, KAVERI)
CHIPSET(0x131C, KAVERI_131C, KAVERI)
CHIPSET(0x131D, KAVERI_131D, KAVERI)
commit f2a1b7d508d0daa71bd97843d67e43108405cff7
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Sat Aug 16 15:18:21 2014 -0700
i965: Disable try_emit_b2f_of_compare on Gen4-6.
The optimization relies on CMP setting the destination to 0, which is
equivalent to 0.0f. However, early platforms only set the least
significant byte, leaving the other bits undefined. So, we must disable
the optimization on those platforms.
Oddly, Sandybridge wasn't reported as broken. The PRM states that it
only sets the LSB, but the internal documentation says that it follows
the IVB behavior. Since it wasn't reported as broken, we believe it
really does follow the IVB behavior.
v2: Allow the optimization on Sandybridge (requested by Matt).
+32 piglits on Ironlake.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Chris Forbes <chr...@ijw.co.nz>
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 97d03b9366bfa55b27feb92aa5afacd9c5f6f421)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index eca5d0c..6e48be7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1135,6 +1135,13 @@ vec4_visitor::try_emit_mad(ir_expression *ir)
bool
vec4_visitor::try_emit_b2f_of_compare(ir_expression *ir)
{
+ /* This optimization relies on CMP setting the destination to 0 when
+ * false. Early hardware only sets the least significant bit, and
+ * leaves the other bits undefined. So we can't use it.
+ */
+ if (brw->gen < 6)
+ return false;
+
ir_expression *const cmp = ir->operands[0]->as_expression();
if (cmp == NULL)
commit 53728f60aa5ddf93579abd0d424eeac545fa57d3
Author: Matt Turner <matts...@gmail.com>
Date: Thu Aug 21 23:02:49 2014 -0700
i965: Fix JIP/UIP calculations.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82846
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82929
(cherry picked from commit d77f5603a5de26e66561ec003118bbfb1a07666b)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 3680c55..4f509dd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -1029,19 +1029,17 @@ update_uip_jip(struct brw_context *brw, brw_inst *insn,
{
int scale = brw->gen >= 8 ? sizeof(brw_compact_inst) : 1;
- int32_t jip = brw_inst_jip(brw, insn);
- jip -= scale *
- compacted_between(this_old_ip, this_old_ip + jip, compacted_counts);
- brw_inst_set_jip(brw, insn, jip);
+ int32_t jip = brw_inst_jip(brw, insn) / scale;
+ jip -= compacted_between(this_old_ip, this_old_ip + jip, compacted_counts);
+ brw_inst_set_jip(brw, insn, jip * scale);
if (brw_inst_opcode(brw, insn) == BRW_OPCODE_ENDIF ||
brw_inst_opcode(brw, insn) == BRW_OPCODE_WHILE)
return;
- int32_t uip = brw_inst_uip(brw, insn);
- uip -= scale *
- compacted_between(this_old_ip, this_old_ip + uip, compacted_counts);
- brw_inst_set_uip(brw, insn, uip);
+ int32_t uip = brw_inst_uip(brw, insn) / scale;
+ uip -= compacted_between(this_old_ip, this_old_ip + uip, compacted_counts);
+ brw_inst_set_uip(brw, insn, uip * scale);
}
void
--
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