configure.ac | 2
src/Makefile.am | 17
src/drmmode_display.c | 31 +
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 ++++++++++++++++++++++++-----------------
src/nouveau_copy.c | 5
src/nouveau_dri2.c | 14
src/nouveau_exa.c | 3
src/nouveau_local.h | 2
src/nouveau_present.c | 6
src/nouveau_xv.c | 4
src/nv_accel_common.c | 2
src/nv_driver.c | 7
src/nv_proto.h | 1
src/nv_type.h | 1
src/nvc0_accel.c | 74 +++
src/nvc0_accel.h | 57 ++
src/nvc0_exa.c | 71 ++-
src/nvc0_xv.c | 115 +++--
src/shader/Makefile | 23 -
src/shader/exac8nv110.fp | 47 ++
src/shader/exac8nv110.fpc | 38 +
src/shader/exacanv110.fp | 47 ++
src/shader/exacanv110.fpc | 38 +
src/shader/exacmnv110.fp | 47 ++
src/shader/exacmnv110.fpc | 38 +
src/shader/exas8nv110.fp | 42 +
src/shader/exas8nv110.fpc | 28 +
src/shader/exasanv110.fp | 47 ++
src/shader/exasanv110.fpc | 38 +
src/shader/exascnv110.fp | 38 +
src/shader/exascnv110.fpc | 20
src/shader/videonv110.fp | 54 ++
src/shader/videonv110.fpc | 52 ++
src/shader/xfrm2nv110.vp | 82 +++
src/shader/xfrm2nv110.vpc | 102 ++++
36 files changed, 1986 insertions(+), 439 deletions(-)
New commits:
commit a7c190e0c230ed2d5e047ed6aba12d71a4866950
Author: Lyude <ly...@redhat.com>
Date: Fri Apr 21 14:41:17 2017 -0400
Bump version to 1.0.15
Signed-off-by: Lyude <ly...@redhat.com>
diff --git a/configure.ac b/configure.ac
index e494300..0b01d3e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ([2.60])
AC_INIT([xf86-video-nouveau],
- [1.0.14],
+ [1.0.15],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-nouveau])
commit 3047e99a641d2b8720371aae292750206f5e91fc
Author: Ben Skeggs <bske...@redhat.com>
Date: Thu Apr 20 15:57:33 2017 +1000
fix null pointer deref when building against >=libdrm 2.4.78
A new pointer got added to drmEventContext.
As a result of us both:
- Setting drmEventContext.version to "latest" AND
- Not zeroing the struct
We end up thwarting libdrm's compatibility checks, resulting in
libdrm choosing to call through an invalid pointer.
Fix this by zeroing the struct.
Signed-off-by: Ben Skeggs <bske...@redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index ae29d9a..2b71c9c 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1433,7 +1433,7 @@ Bool drmmode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp)
unsigned int crtcs_needed = 0;
int crtcshift;
- drmmode = xnfalloc(sizeof *drmmode);
+ drmmode = xnfcalloc(sizeof(*drmmode), 1);
drmmode->fd = fd;
drmmode->fb_id = 0;
commit e9418e434311336e905b70553a5ed740838d90ad
Author: Mariusz Bialonczyk <ma...@skyboo.net>
Date: Wed Mar 29 22:07:50 2017 +0200
Do not register hotplug without RandR
When using Xinerama, RandR is automatically disabled, and calling RR
routines will trigger an assert() because the RR keys/resources are
not set, leading to an Xserver abort.
Hotplug makes little sense without RandR, so no need to install a
udev monitor if RandR is not available.
Ported from xf86-video-intel commit
1a489142c8e6a4828348cc9afbd0f430d3b1e2d8, original work by:
Chris Wilson <ch...@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98383
Signed-off-by: Mariusz Bialonczyk <ma...@skyboo.net>
Acked-by: Ilia Mirkin <imir...@alum.mit.edu>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index dd9fa27..ae29d9a 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1556,6 +1556,15 @@ drmmode_udev_notify(int fd, int notify, void *data)
}
#endif
+static bool has_randr(void)
+{
+#if HAS_DIXREGISTERPRIVATEKEY
+ return dixPrivateKeyRegistered(rrPrivKey);
+#else
+ return *rrPrivKey;
+#endif
+}
+
static void
drmmode_uevent_init(ScrnInfoPtr scrn)
{
@@ -1564,6 +1573,12 @@ drmmode_uevent_init(ScrnInfoPtr scrn)
struct udev *u;
struct udev_monitor *mon;
+ /* RandR will be disabled if Xinerama is active, and so generating
+ * RR hotplug events is then forbidden.
+ */
+ if (!has_randr())
+ return;
+
u = udev_new();
if (!u)
return;
commit e472b47d15634a864c8c981ed588d882aceaf26b
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Tue Mar 21 21:25:33 2017 -0400
Add Pascal family support, identical to Maxwell
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Tested-by: Lyude <ly...@redhat.com>
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index 7118a7a..7fbcc87 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,7 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {
+ { 0xc1b5, 0, nouveau_copya0b5_init },
{ 0xc0b5, 0, nouveau_copya0b5_init },
{ 0xb0b5, 0, nouveau_copya0b5_init },
{ 0xa0b5, 0, nouveau_copya0b5_init },
@@ -84,6 +85,7 @@ nouveau_copy_init(ScreenPtr pScreen)
break;
case NV_KEPLER:
case NV_MAXWELL:
+ case NV_PASCAL:
ret = nouveau_object_new(&pNv->dev->object, 0,
NOUVEAU_FIFO_CHANNEL_CLASS,
&(struct nve0_fifo) {
diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c
index 0f02b99..55df6f8 100644
--- a/src/nouveau_exa.c
+++ b/src/nouveau_exa.c
@@ -515,6 +515,7 @@ nouveau_exa_init(ScreenPtr pScreen)
case NV_FERMI:
case NV_KEPLER:
case NV_MAXWELL:
+ case NV_PASCAL:
exa->CheckComposite = NVC0EXACheckComposite;
exa->PrepareComposite = NVC0EXAPrepareComposite;
exa->Composite = NVC0EXAComposite;
diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c
index 5d12dd8..5561708 100644
--- a/src/nv_accel_common.c
+++ b/src/nv_accel_common.c
@@ -723,6 +723,7 @@ NVAccelCommonInit(ScrnInfoPtr pScrn)
case NV_FERMI:
case NV_KEPLER:
case NV_MAXWELL:
+ case NV_PASCAL:
INIT_CONTEXT_OBJECT(3D_NVC0);
break;
case NV_TESLA:
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 61940a8..32062eb 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -391,6 +391,7 @@ NVHasKMS(struct pci_device *pci_dev, struct
xf86_platform_device *platform_dev)
case 0x100:
case 0x110:
case 0x120:
+ case 0x130:
break;
default:
xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset);
@@ -945,6 +946,9 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
case 0x120:
pNv->Architecture = NV_MAXWELL;
break;
+ case 0x130:
+ pNv->Architecture = NV_PASCAL;
+ break;
default:
return FALSE;
}
diff --git a/src/nv_type.h b/src/nv_type.h
index d7bb4f4..6dc5793 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -23,6 +23,7 @@
#define NV_FERMI 0xc0
#define NV_KEPLER 0xe0
#define NV_MAXWELL 0x110
+#define NV_PASCAL 0x130
struct xf86_platform_device;
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 6c2bae8..1047d36 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -250,6 +250,12 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0x130) {
class = 0xb197;
handle = 0x0000906e;
+ } else if (pNv->dev->chipset == 0x130) {
+ class = 0xc097;
+ handle = 0x0000906e;
+ } else if (pNv->dev->chipset < 0x140) {
+ class = 0xc197;
+ handle = 0x0000906e;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"No 3D acceleration support for NV%X\n",
commit b71de83b7fae0abeb311251e6144294d319062cf
Author: Lyude <ly...@redhat.com>
Date: Tue Mar 7 18:44:43 2017 -0500
Bump version to 1.0.14
Signed-off-by: Lyude <ly...@redhat.com>
diff --git a/configure.ac b/configure.ac
index 0e004d7..e494300 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ([2.60])
AC_INIT([xf86-video-nouveau],
- [1.0.13],
+ [1.0.14],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-nouveau])
commit 924083938c8f209d8f6ff472caf8692a644f7e78
Author: Lyude <ly...@redhat.com>
Date: Fri Mar 3 18:27:42 2017 -0500
Consider CRTCs disabled when DPMS is off
It turns out there's a difference in X between a CRTC being "disabled"
and simply having it's DPMS turned off. This is problematic though,
because if DPMS is turned off you can't really use the CRTC as a normal
CRTC anyway since page flipping and vblanks will be non-functional. As a
result, we've been considering DPMS-on CRTCs as enabled and attempt to
perform pageflips, vblank waits, etc. on them which inevitably fails. and
usually breaks the display the first time any of the CRTCs have their
DPMS turned on.
This was a problem that didn't really show itself until kernel 4.10 when
atomic modesetting was added which caused nouveau to stop trying to
fulfill pageflips and vblank waits on disabled CRTCs. I'm not sure how
pageflipping disabled CRTCs ever worked in the first place, but since
not doing so is the proper behavior anyway I haven't investigated any
further.
So, copy the ms_crtc_on() function from the modesetting driver and add
it here as drmmode_crtc_on(), then use that in all of the places where
we should be checking for both DPMS off and disabled CRTCs.
This fixes issues with the X ceasing to function (usually) after the
first time a CRTC has it's DPMS turned on. Reproduction recipe:
- Load up gnome-shell on a machine
- Wait for the display to timeout from inactivity and turn itself off
- Shake the cursor or press something on the keyboard. Chances are the
monitor will come back on, but the display remains black until the
next time the X server is restarted.
Signed-off-by: Lyude <ly...@redhat.com>
Reviewed-by: Adam Jackson <a...@redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b6c9bb9..dd9fa27 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -65,6 +65,7 @@ typedef struct {
uint32_t rotate_fb_id;
Bool cursor_visible;
int scanout_pixmap_x;
+ int dpms_mode;
} drmmode_crtc_private_rec, *drmmode_crtc_private_ptr;
typedef struct {
@@ -114,6 +115,14 @@ drmmode_crtc(xf86CrtcPtr crtc)
return drmmode_crtc->mode_crtc->crtc_id;
}
+Bool
+drmmode_crtc_on(xf86CrtcPtr crtc)
+{
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+ return crtc->enabled && drmmode_crtc->dpms_mode == DPMSModeOn;
+}
+
int
drmmode_head(xf86CrtcPtr crtc)
{
@@ -313,9 +322,10 @@ drmmode_ConvertToKMode(ScrnInfoPtr scrn, drmModeModeInfo
*kmode,
}
static void
-drmmode_crtc_dpms(xf86CrtcPtr drmmode_crtc, int mode)
+drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
-
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+ drmmode_crtc->dpms_mode = mode;
}
void
diff --git a/src/nouveau_dri2.c b/src/nouveau_dri2.c
index 81ee9be..cbb7b2a 100644
--- a/src/nouveau_dri2.c
+++ b/src/nouveau_dri2.c
@@ -279,23 +279,27 @@ can_exchange(DrawablePtr draw, PixmapPtr dst_pix,
PixmapPtr src_pix)
ScrnInfoPtr scrn = xf86ScreenToScrn(draw->pScreen);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
NVPtr pNv = NVPTR(scrn);
- int i;
+ int i, active_crtc_count = 0;
if (!xf86_config->num_crtc)
return FALSE;
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- if (crtc->enabled && crtc->rotatedData)
- return FALSE;
+ if (drmmode_crtc_on(crtc)) {
+ if (crtc->rotatedData)
+ return FALSE;
+ active_crtc_count++;
+ }
}
return ((DRI2CanFlip(draw) && pNv->has_pageflip)) &&
dst_pix->drawable.width == src_pix->drawable.width &&
dst_pix->drawable.height == src_pix->drawable.height &&
dst_pix->drawable.bitsPerPixel ==
src_pix->drawable.bitsPerPixel &&
- dst_pix->devKind == src_pix->devKind;
+ dst_pix->devKind == src_pix->devKind &&
+ active_crtc_count;
}
static Bool
@@ -475,7 +479,7 @@ dri2_page_flip(DrawablePtr draw, PixmapPtr back, void *priv,
int head = drmmode_crtc(config->crtc[i]);
void *token;
- if (!config->crtc[i]->enabled)
+ if (!drmmode_crtc_on(config->crtc[i]))
continue;
flipdata->flip_count++;
diff --git a/src/nouveau_present.c b/src/nouveau_present.c
index 482ac6e..ebd5fcf 100644
--- a/src/nouveau_present.c
+++ b/src/nouveau_present.c
@@ -152,7 +152,7 @@ nouveau_present_flip_check(RRCrtcPtr rrcrtc, WindowPtr
window,
ScrnInfoPtr scrn = xf86ScreenToScrn(window->drawable.pScreen);
xf86CrtcPtr crtc = rrcrtc->devPrivate;
- if (!scrn->vtSema || !crtc->enabled)
+ if (!scrn->vtSema || !drmmode_crtc_on(crtc))
return FALSE;
return TRUE;
@@ -199,7 +199,7 @@ nouveau_present_flip_exec(ScrnInfoPtr scrn, uint64_t
event_id, int sync,
flip->msc = target_msc;
for (i = 0; i < config->num_crtc; i++) {
- if (config->crtc[i]->enabled)
+ if (drmmode_crtc_on(config->crtc[i]))
last = i;
}
@@ -208,7 +208,7 @@ nouveau_present_flip_exec(ScrnInfoPtr scrn, uint64_t
event_id, int sync,
int crtc = drmmode_crtc(config->crtc[i]);
void *user = NULL;
- if (!config->crtc[i]->enabled)
+ if (!drmmode_crtc_on(config->crtc[i]))
continue;
if (token && ((crtc == sync) || (i == last))) {
diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index 716b18d..4b939f7 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -299,7 +299,7 @@ nv_window_belongs_to_crtc(ScrnInfoPtr pScrn, int x, int y,
int w, int h)
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- if (!crtc->enabled)
+ if (!drmmode_crtc_on(crtc))
continue;
if ((x < (crtc->x + crtc->mode.HDisplay)) &&
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 122ede5..4a57406 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -13,6 +13,7 @@ void drmmode_screen_init(ScreenPtr pScreen);
void drmmode_screen_fini(ScreenPtr pScreen);
int drmmode_crtc(xf86CrtcPtr crtc);
+Bool drmmode_crtc_on(xf86CrtcPtr crtc);
int drmmode_head(xf86CrtcPtr crtc);
void drmmode_swap(ScrnInfoPtr, uint32_t, uint32_t *);
commit 1516d35b06c9cda399bef01d992805d6e63dcbae
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Oct 16 15:10:10 2016 -0400
recognize and accelerate GM20x
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/nv_driver.c b/src/nv_driver.c
index fff83f8..61940a8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct
xf86_platform_device *platform_dev)
case 0xf0:
case 0x100:
case 0x110:
+ case 0x120:
break;
default:
xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset);
@@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->Architecture = NV_KEPLER;
break;
case 0x110:
+ case 0x120:
pNv->Architecture = NV_MAXWELL;
break;
default:
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index d0a835e..6c2bae8 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -244,9 +244,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0x110) {
class = 0xa197;
handle = 0x0000906e;
- } else {
+ } else if (pNv->dev->chipset < 0x120) {
class = 0xb097;
handle = 0x0000906e;
+ } else if (pNv->dev->chipset < 0x130) {
+ class = 0xb197;
+ handle = 0x0000906e;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "No 3D acceleration support for NV%X\n",
+ pNv->dev->chipset);
+ return FALSE;
}
ret = nouveau_object_new(pNv->channel, class, class,
commit b00b73c3aa0da1d4cee5c9f580ca65a7bd344e0f
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Mon Oct 17 23:23:41 2016 -0400
copy: add maxwell/pascal copy engine classes
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index c139de6..7118a7a 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {
+ { 0xc0b5, 0, nouveau_copya0b5_init },
+ { 0xb0b5, 0, nouveau_copya0b5_init },
{ 0xa0b5, 0, nouveau_copya0b5_init },
{ 0x90b8, 5, nouveau_copy90b5_init },
{ 0x90b5, 4, nouveau_copy90b5_init },
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 8da5051..d0a835e 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
struct nouveau_pushbuf *push = pNv->pushbuf;
+ uint32_t class;
int ret;
- ret = nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5,
+ if (pNv->dev->chipset < 0x110)
+ class = 0xa0b5;
+ else if (pNv->dev->chipset < 0x130)
+ class = 0xb0b5;
+ else
+ class = 0xc0b5;
+
+ ret = nouveau_object_new(pNv->channel, class, class,
NULL, 0, &pNv->NvCOPY);
if (ret)
return FALSE;
commit 5a3ada3b0ff3d89441faf35d331bb8b6cf5e51c0
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Oct 16 15:03:35 2016 -0400
nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo
*bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
+ unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x00004000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x00300000);
+ PUSH_DATA(push, 0x80000000 | width);
+ PUSH_DATA(push, 0x00010000 | height);
+ PUSH_DATA(push, 0x03000000);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push,
GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0xffff));
+ PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO
|
+
GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
(height - 1));
+ PUSH_DATA(push, 0x000000000);
+ PUSH_DATA(push, 0x000000000);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index d3fd316..b396079 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr pdpict,
int op)
static Bool
NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
{
- uint64_t offset = pNv->scratch->offset + SOLID(unit);
struct nouveau_pushbuf *push = pNv->pushbuf;
PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
- PUSH_DATA (push, offset);
- PUSH_DATA (push, (offset >> 32) | 0xd005d000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, 0x00000001);
- PUSH_DATA (push, 0x00010001);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, pNv->scratch, SOLID(unit), 1, 1, 4,
+ _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
NV50TSC_1_0_WRAPT_REPEAT |
@@ -651,16 +644,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr
ppict, unsigned unit)
PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, format);
- PUSH_DATA (push, bo->offset);
- PUSH_DATA (push, (bo->offset >> 32) |
- (bo->config.nvc0.tile_mode << 18) |
- 0xd0005000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (1 << 31) | ppix->drawable.width);
- PUSH_DATA (push, (1 << 16) | ppix->drawable.height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
+ format);
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
if (ppict->repeat) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 2d66fa8..5cecbf5 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y2;
BoxPtr pbox;
int nbox;
@@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
if (id == FOURCC_YV12 || id == FOURCC_I420) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, packed_y, width, height, 0,
+ NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8);
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
+ NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8_8);
- PUSH_DATA (push, ((src->offset + uv)));
- PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width >> 1);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
} else {
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ unsigned format;
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width, height, 0, format);
+
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (width >> 1));
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ NV50TIC_0_0_FMT_8_8_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format);
}
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16);
commit 514441f32c5b948ce87668234ab9f01e8ec28dac
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Oct 16 12:42:18 2016 -0400
nvc0: rename BEGIN_IMC0 to IMMED_NVC0
For consistency with mesa. It wasn't used anywhere previously.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/nouveau_local.h b/src/nouveau_local.h
index 3de69a2..dd49395 100644
--- a/src/nouveau_local.h
+++ b/src/nouveau_local.h
@@ -237,7 +237,7 @@ BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int
mthd, int size)
}
static inline void
-BEGIN_IMC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
+IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
{
PUSH_DATA (push, 0x80000000 | (data << 16) | (subc << 13) | (mthd / 4));
}
commit 4459c04a6bc208924fac8082920f6786538bc5cd
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Oct 16 12:38:38 2016 -0400
nvc0: make use of the new hwdefs for TEX_CB_INDEX
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 52a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1);
PUSH_DATA (push, 0x11);
- BEGIN_NVC0(push, SUBC_3D(0x2608), 1);
+ BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
PUSH_DATA (push, 1);
}
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 4c3bb0f..607e97b 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -12,6 +12,7 @@
/* subchannel assignments, compatible with kepler's fixed layout */
#define SUBC_3D(mthd) 0, (mthd)
#define NVC0_3D(mthd) SUBC_3D(NVC0_3D_##mthd)
+#define NVE4_3D(mthd) SUBC_3D(NVE4_3D_##mthd)
#define SUBC_M2MF(mthd) 2, (mthd)
#define SUBC_P2MF(mthd) 2, (mthd)
#define NVC0_M2MF(mthd) SUBC_M2MF(NVC0_M2MF_##mthd)
commit ea6fd12ea059c6af832bd2180b26d75e00d4ea71
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Oct 16 12:38:02 2016 -0400
hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
diff --git a/src/Makefile.am b/src/Makefile.am
index 6ba8d87..d777fe5 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -71,6 +71,7 @@ EXTRA_DIST = hwdefs/nv_3ddefs.xml.h \
hwdefs/nv50_texture.h \
hwdefs/nvc0_3d.xml.h \
hwdefs/nvc0_m2mf.xml.h \
+ hwdefs/gm107_texture.xml.h \
shader/exac8nvc0.fp \
shader/exac8nvc0.fpc \
shader/exac8nve0.fp \
diff --git a/src/hwdefs/gm107_texture.xml.h b/src/hwdefs/gm107_texture.xml.h
new file mode 100644
index 0000000..a4bc380
--- /dev/null
+++ b/src/hwdefs/gm107_texture.xml.h
@@ -0,0 +1,365 @@
+#ifndef GM107_TEXTURE_XML
+#define GM107_TEXTURE_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git
repository:
+http://github.com/envytools/envytools/
+git clone https://github.com/envytools/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/gm107_texture.xml ( 22057
bytes, from 2016-02-12 03:01:43)
+- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456
bytes, from 2015-09-10 02:57:40)
+- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908
bytes, from 2016-02-04 22:19:11)
+- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739
bytes, from 2016-02-04 00:29:42)
+
+Copyright (C) 2006-2016 by the following authors:
+- Artur Huillet <arthur.huil...@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala...@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlo...@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425...@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajow...@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lu...@users.sf.net> (lumag)
+- EdB <e...@users.sf.net> (edb_)
+- Erik Waling <erikwail...@users.sf.net> (erikwaling)
+- Francisco Jerez <curroje...@riseup.net> (curro)
+- Ilia Mirkin <imir...@alum.mit.edu> (imirkin)
+- jb17bsome <jb17bs...@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjer...@users.sf.net> (kjeremy)
+- Laurent Carlier <lordhea...@gmail.com> (lordheavy)
+- Luca Barbieri <l...@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2...@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koria...@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.ca...@gmail.com> (careym)
+- Matthieu Castet <matthieu.cas...@parrot.com> (mat-c)
+- nvidiaman <nvidia...@users.sf.net> (nvidiaman)
+- Patrice Mandin <patman...@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <p...@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpe...@users.sf.net> (ironpeter)
+- Richard Hughes <hughsi...@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilib...@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <lerout...@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marche...@gmail.com> (marcheu)
+- sturmflut <sturmf...@users.sf.net> (sturmflut)
+- Sylvain Munaut <t...@246tnt.com>
+- Victor Stinner <victor.stin...@haypocalc.com> (haypo)
+- Wladmir van der Laan <laa...@gmail.com> (miathan6)
+- Younes Manton <youne...@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define GM107_TIC2__SIZE 0x00000020
+#define GM107_TIC2_0 0x00000000
+#define GM107_TIC2_0_COMPONENTS_SIZES__MASK 0x0000007f
+#define GM107_TIC2_0_COMPONENTS_SIZES__SHIFT 0
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32 0x00000002
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32 0x00000004
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_B24G8
0x00000005
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8B8G8R8 0x00000007
+#define GM107_TIC2_0_COMPONENTS_SIZES_A8B8G8R8 0x00000008
+#define GM107_TIC2_0_COMPONENTS_SIZES_A2B10G10R10 0x00000009
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16 0x0000000c
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R24 0x0000000d
+#define GM107_TIC2_0_COMPONENTS_SIZES_G24R8 0x0000000e
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32 0x0000000f
+#define GM107_TIC2_0_COMPONENTS_SIZES_A4B4G4R4 0x00000012
+#define GM107_TIC2_0_COMPONENTS_SIZES_A5B5G5R1 0x00000013
+#define GM107_TIC2_0_COMPONENTS_SIZES_A1B5G5R5 0x00000014
+#define GM107_TIC2_0_COMPONENTS_SIZES_B5G6R5 0x00000015
+#define GM107_TIC2_0_COMPONENTS_SIZES_B6G5R5 0x00000016
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R8 0x00000018
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16 0x0000001b
