Timo Aaltonen pushed to branch upstream-experimental at X Strike Force / lib / mesa
Commits: b32eb098 by Eric Engestrom at 2026-04-29T17:53:10+02:00 .pick_status.json: Update to d4d7055aee547f452689f8165e21ca100869e6fe Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - e65c1667 by Tapani Pälli at 2026-04-29T17:53:10+02:00 drirc/anv: add flag to disable VK_EXT_subgroup_size_control This can be used to workaround problem cases with application controlled subgroup size. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit c105366165ae85c4417a9674e073496cbed1f932) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 2c9c3798 by Tapani Pälli at 2026-04-29T17:53:10+02:00 drirc: set anv_disable_subgroup_size_control for bg3 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15225 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/14501 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 4394e26f5270972028be44af6436b898688f7ee4) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - c95cabc0 by Valentine Burley at 2026-04-29T17:53:10+02:00 zink/ci: Remove Cezanne job The devices will be repurposed for a different job. Signed-off-by: Valentine Burley <[email protected]> (cherry picked from commit 4e4207e639444c98e59c1834453eb5072e4ac94b) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 02c2fe83 by Tapani Pälli at 2026-04-29T17:53:10+02:00 drirc: use anv_disable_drm_ccs_modifiers for any GTK version Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15297 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit a76e3c26164aa4b281146f89cc9ffe4dea83965b) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - b9e1ed02 by David Rosca at 2026-04-29T17:53:10+02:00 radv/video: Fix initializing rc structs with default rate control Fixes: 32a02720a88 ("radv/video: Init session and update rate control in ControlVideoCoding") Reviewed-by: Benjamin Cheng <[email protected]> (cherry picked from commit 3d0239cff9300e81af2e45bc0571077fe4ab3e71) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 4a330b69 by Lars-Ivar Hesselberg Simonsen at 2026-04-29T17:53:10+02:00 panvk: Fix debug flag overlap PANVK_DEBUG_HSR_PREPASS and PANVK_DEBUG_NO_EXTENDED_VA_RANGE have the same value, meaning they both get toggled when one is. This commit moves PANVK_DEBUG_HSR_PREPASS to the following value. Fixes: 2d9be417065 ("panvk/v13: Support HSR Prepass") Reviewed-by: John Anthony <[email protected]> (cherry picked from commit 82592433e605cdaa8d2e0593eba0353254e9500e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 99e944d0 by GKraats at 2026-04-29T17:53:10+02:00 crocus: Fix shader precompilation on Gen6 and higher By default crocus precompiles shaders, to avoid stuttering at screens, caused by compiling shaders at the drawing phase. Unfortunately at intel Gen 6 and higher the precompiled version of the fragment shaders is not used and every fragment shader is compiled twice. These double fragment shaders also are added to the memory cache and disk cache. This is caused by setting wrong values to variables at the key during precompiling at routine crocus_create_fs_state() at src/gallium/drivers/crocus/crocus_program.c, which differ from values at crocus_populate_fs_key() at src/gallium/drivers/crocus/crocus_state.c. This commit solves 3 problems: it adjusts the predicted value 'input_slots_valid' at Gen 6 it adjusts the predicted value 'ignore_sample_mask_out' at Gen 6 and higher it predicts the value 'multisample_fbo' , which helps if samplemask is used Cc: mesa-stable Signed-off-by: GKraats <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 686266d2f1aae3027fd039386c166ce3fadfce7f) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 7b319438 by Qiang Yu at 2026-04-29T17:53:10+02:00 ac,radeonsi,radv: fix print IB assertion fail for reserved fields New IB print will assert reserved packet field to be zero. Fixes: 1c75cd958f4 ("ac: enable the new auto-generated CP packet parser") Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 89c1bf34ede1a3cf4f5008255ad5ab4131581801) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 82d5a689 by Valentine Burley at 2026-04-29T17:53:10+02:00 tu/drm/virtio: Fix tu_wait_fence timeout handling Fixes two bugs in the WAIT_FENCE polling loop: 1. Break on timeout returned VK_SUCCESS because ret was read too late. 2. UINT64_MAX timeout_ns overflowed end_time, causing immediate exit. Fix by reading rsp->ret before the timeout check and using OS_TIMEOUT_INFINITE (like virtio_pipe_wait in freedreno) to avoid overflow. This prevents premature BO teardown during host-side fault recovery. Fixes: f17c5297d7a ("tu: Add virtgpu support") Signed-off-by: Valentine Burley <[email protected]> (cherry picked from commit dad72b414b14764dd868eb2e5832aab3dd473982) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - a10b6edc by Valentine Burley at 2026-04-29T17:53:10+02:00 freedreno/drm/virtio: Fix wait_fence ret ordering ret was read after the timeout check, so breaking on timeout returned 0 instead of the actual fence status, potentially reporting a signaled fence when it was still pending. Fixes: 441f01e7781 ("freedreno/drm/virtio: Drop blocking in host") Signed-off-by: Valentine Burley <[email protected]> (cherry picked from commit 97baa27dadf6d1df9d1bbaf9f9806a7b219e21dc) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 905e8efa by Liu, Mengyang at 2026-04-29T17:53:10+02:00 aco: fix broken VGPRs reservation for 64-bit attributes in VS prologs After 8e6bff4caac2, the large attribute counts as two slots in `num_attributes` if the vertex shader consumes more than two channels of it, even though `misaligned_mask` marks only the lower slot. Fixes: 8e6bff4caac2 ("radv: Lower 64-bit VS inputs to 32-bit") (cherry picked from commit 40fa195cd0d5539c871c0c6d174660a58ddd5add) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 10aea75a by Christoph Pillmayer at 2026-04-29T17:53:10+02:00 pan/bi: Fix source swizzle in bi_repair_ssa Repairing SSA was creating invalid PHI nodes with source swizzles != BI_SWIZZLE_H01. PHI sources can't have non-identity swizzles. In most cases the repair logic only replaces sources, in which case the swizzle is taken from the old source that is getting replaced. However, in add_phi_operands there is no old source because the phi is new, and so the result from resolve_read is assigned directly. This falsely carries over the destination swizzle to the source. Since it never makes sense for resolve_read to carry over the swizzle from the instruction writing the value, we can make it so that resolve_read always returns the identity swizzle on indices. resolve_read returns one of: - An index stored by record_write - An index created by bi_temp_like - The result of a recursive resolve_read call bi_temp_like already correctly sets the swizzle to H01. Setting it in record_write leads to both base cases returning the desired swizzle. Fixes: dd94d183 ("pan/bi: Fixup bi_repair_ssa.c for bi") Reviewed-by: Lorenzo Rossi <[email protected]> Reviewed-by: Eric R. Smith <[email protected]> (cherry picked from commit fcfc580f67d2a5f1a5cb84072d4fd028661f01a0) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 97044c1f by Dave Airlie at 2026-04-29T17:53:10+02:00 nouveau: drop sector promotion. Just like the fix for nvk, just drop this in the GL driver as well. Cc: mesa-stable Reviewed-by: Karol Herbst <[email protected]> Reviewed-by: Mel Henning <[email protected]> (cherry picked from commit 3f5d54ab8ca608566a75900d22b909ad84925c44) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 54201c5d by Duncan Brawley at 2026-04-29T17:53:10+02:00 pco: Fix pco_last_igrp returning the first element instead of the last Because of a previous refactor, pco_last_igrp was incorrectly changed to return the first entry in a linked list instead of the last. Update pco_last_igrp to return the last entry in a linked list. The following CTS tests now pass: dEQP-GLES3.functional.shaders.switch.conditional_fall_through_2_dynamic_fragment dEQP-GLES3.functional.shaders.switch.conditional_fall_through_dynamic_fragment dEQP-GLES3.functional.shaders.switch.conditional_fall_through_uniform_fragment Fixes: 719ece42c0d ("pco: Switch back to util/list") Signed-off-by: Duncan Brawley <[email protected]> Reviewed-by: Frank Binns <[email protected]> (cherry picked from commit 7428af29f6d8aeac7f441a00f16a8fb4b8cac257) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 5bba1d9b by Matt Turner at 2026-04-29T17:53:11+02:00 radv: fix UB in radv_format_pack_clear_color for snorm formats Casting a negative float to uint64_t is undefined behavior. GCC 15 with -O2 produces 0xFFFFFFFFFFFFFFFF for (uint64_t)(-32767.5f), causing snorm clear values to be packed incorrectly (e.g. 0xFFFF instead of 0x8001 for snorm16 -1.0). This results in wrong DCC comp-to-single clear colors and ~966 CTS snorm multisample_resolve test failures. Fix by casting through int64_t first, which is well-defined (truncation toward zero) and preserves the two's complement bit pattern. Fixes: 585c25be1e1 ("radv: fix color conversions for normalized uint/sint formats") Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 2595940b0def52f1eb9d3e8aadb88e3e363afe5c) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 570c5a78 by Derek Lesho at 2026-04-29T17:53:11+02:00 zink: Guard bo map/unmap on map_count. Otherwise zink_bo_map can return cpu_ptr being destroyed by zink_bo_unmap. Cc: mesa-stable (cherry picked from commit ce45069c49cdc0eb5c1bb14a548740de23cd1908) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 8c8755b2 by Silvio Vilerino at 2026-04-29T17:53:11+02:00 Revert "d3d12: Video sliced encode: Use same ID3D12Fence/different per slice values as optimization" This reverts commit b83a931cb17567e878b1fb135f8f12736b37ca13 as it causes regressions with dirty rects enabled on some HW platforms that signal out of order completion and require individual fence objects per slice Fixes: b83a931cb17 ("d3d12: Video sliced encode: Use same ID3D12Fence/different per slice values as optimization") Reviewed-by: Pohsiang (John) Hsu <[email protected]> (cherry picked from commit fb13c044a8b6dd9c0a54df8ffd75792b2ad78f9e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 7553e830 by Samuel Pitoiset at 2026-04-29T17:53:11+02:00 radv: re-introduce DGC+multiview support and enable it for vkd3d-proton only The Vulkan spec says: "VUID-vkCmdExecuteGeneratedCommandsEXT-None-11062 If a rendering pass is currently active, the view mask must be 0." So, it's invalid with VK_EXT_device_generated_commands but it's allowed in DX12, it seems we missed this during the spec review. Crimson Desert uses this and emulating in vkd3d-proton would be complex, so let's re-introduce this support only for vkd3d-proton. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 782254b820f4e4c73eb680b6e702a3688ae844d8) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 0dd2d436 by Faith Ekstrand at 2026-04-29T17:53:11+02:00 panvk/csf: Emit INDEX_BUFFER[_SIZE] even for non-indexed draws The index buffer and index buffer size don't affect whether or not we're actually doing indexed rendering so we should just emit them whenever they change. Otherwise, if someone sets an index buffer and then does a non-indexed draw and then an indexed draw, the first draw will clear the dirty bits without setting the index buffer registers and the second draw won't know to re-emit them. Fixes: 5544d39f4420 ("panvk: Add a CSF backend for panvk_queue/cmd_buffer") Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]> Reviewed-by: Marc Alcala Prieto <[email protected]> (cherry picked from commit 9c8e8ed655376a1a90c0d879dc40d2cc4a6f63c5) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 05c54411 by Simon Perretta at 2026-04-29T17:53:11+02:00 pco: reserve additional outputs for trilinear sampled coeffs Sampling coeffs with trilinear filtering will output 2x sets of data. Whether bilinear or trilinear filtering is in use can't be determined without checking state words, so unconditionally reserve 2x to avoid clobbering output regs. Fixes: 7df32ba09d3 ("pco: initial texture/sampler compiler support") Signed-off-by: Simon Perretta <[email protected]> Acked-by: Frank Binns <[email protected]> Tested-by: Icenowy Zheng <[email protected]> (cherry picked from commit af1669d9e25a346104d061ec05e89bd6a5a80c40) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - b771d69b by Pavel Ondračka at 2026-04-29T17:53:11+02:00 r300: fix MSAA resolve COLORPITCH tiling after pipe_surface de-pointerization r300_simple_msaa_resolve used to patch srcsurf->pitch with the resolve destination's tiling bits before passing the surface to the blitter. That worked when set_framebuffer_state kept the same pipe_surface pointer, so r300_get_nonnull_cb returned the patched object. After the de-pointerization, r300_framebuffer_init creates a fresh r300_surface from the pipe_surface template, discarding the pitch modification. The hardware then uses the MSAA source tiling for R300_RB3D_COLORPITCH0, leading to corruption. Move the tiling override into r300_emit_fb_state and override the tiling bits of COLORPITCH from the destination surface at emit time. Fixes: 2eb45daa9c86 ("gallium: de-pointerize pipe_surface") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15303 (cherry picked from commit 416da54cce8782227d44d6dffbb0f99860f9725f) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 3ed36f93 by Jesse Natalie at 2026-04-29T17:53:11+02:00 wgl: Use an hwnd xor hdc for framebuffers It seems maybe hdcs can get recycled? Fixes: 28058221 ("wgl: Support contexts created from non-window DCs") (cherry picked from commit 3f35e6525323d8f51a670dd4b3eb970664beef5e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 2730f538 by Pavel Ondračka at 2026-04-29T17:53:11+02:00 r300: dirty VS state when switching variants When r300_pick_vertex_shader switches to a WPOS variant, it only dirtied rs_block_state, leaving vs_state with a stale code size. This caused cs_count warnings (offset of -4 for one extra VS instruction) but was mostly harmless since the emitted packet stream still used the current shader. Factor the VS code dirtying out of r300_bind_vs_state into a helper and call it when selecting a new variant too. Fixes: 806dcf9db7c ("r300: only output wpos in vertex shaders when needed") (cherry picked from commit cc7be8433a84557740cbc8e095a93afef860a0f3) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 3d8f8d6f by David Rosca at 2026-04-29T17:53:11+02:00 frontends/va: Fix finding LTRs from POCs in HEVC decode This should only consider valid entries, not loop over the entire array. In addition the array size was wrong before. Fixes: 779edc07598 ("frontends/va: Correctly derive HEVC StCurrBefore, StCurrAfter and LtCurr") Reviewed-by: Benjamin Cheng <[email protected]> (cherry picked from commit c2a4fa33b8796c154b3ccd97162f849ea543c343) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 0324fc92 by Timothy Arceri at 2026-04-29T17:53:11+02:00 amd/radeonsi: dont clamp packed user varyings ac_nir_optimize_outputs() might pack user varyings into the color built-ins. If this happens we skip adding clamping to the components that contain the user varying. This change also fixes a second bug where a color built-in can be packed into a non-color slot and was no longer being clamped. Fixes: 3777a5d7 ("radeonsi: assign param export indices before compilation") Closes: #14443 Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit a42c55da46fc8a3846b873231887073a57f39d56) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 13a2d150 by Arjob Mukherjee at 2026-04-29T17:53:11+02:00 pvr: increase value of maxPerStageDescriptorStorageBuffers Increase past the minimum required by the Vulkan Spec to fix tests. This was needed due to Zink requirements which splits `maxPerStageDescriptorStorageBuffers` between atomic buffers and `MaxShaderStorageBlocks`. Fixes the following GLES conformance tests: KHR-GLES31.core.compute_shader.resources-max KHR-GLES31.core.draw_indirect.advanced-twoPass-Compute-arrays KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray KHR-GLES31.core.shader_image_load_store.basic-allTargets-store-cs KHR-GLES31.core.shader_image_load_store.basic-allTargets-store-fs KHR-GLES31.core.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-int KHR-GLES31.core.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case1-cs KHR-GLES31.core.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case2-cs dEQP-GLES31.functional.draw_indirect.compute_interop.combined.drawelements_compute_cmd_and_data_and_indices dEQP-GLES31.functional.synchronization.in_invocation.ssbo_alias_overwrite dEQP-GLES31.functional.synchronization.in_invocation.ssbo_alias_write dEQP-GLES31.functional.synchronization.in_invocation.ssbo_atomic_alias_overwrite dEQP-GLES31.functional.synchronization.in_invocation.ssbo_atomic_alias_write dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_atomic_multiple_write_read dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_multiple_write_read dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_alias_overwrite dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_alias_write dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_alias_overwrite dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_alias_write Backport-to: 26.0 Signed-off-by: Arjob Mukherjee <[email protected]> Reviewed-by: Frank Binns <[email protected]> (cherry picked from commit 35f57a27396c116fc5e9984ac1254d26b83ad2c4) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - cf1752d2 by Simon Perretta at 2026-04-29T17:53:11+02:00 pco: amend tg4 lowering Use lower_tg4_offsets to take care of explicit offsets, and just swizzle the texels in the order defined by textureGather* Fixes: 46c9239c111 ("pvr, pco: initial texture gather support with gather sampler") Signed-off-by: Simon Perretta <[email protected]> Acked-by: Frank Binns <[email protected]> (cherry picked from commit 56b8dc92a96c264549dfed368ccec919879c20dd) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - a3e7443e by Nick Hamilton at 2026-04-29T17:53:11+02:00 pco: fix clamping the array index when shaderImageGatherExtended is enabled The array index value is a signed integer but the compiler was using the unsigned version of the clamp helper function meaning the value was not been clamped to 0 when its value was < 0. Fix the following deqp test cases when shaderImageGatherExtended is enabled dEQP-VK.glsl.texture_gather.basic.2d_array.* dEQP-VK.glsl.texture_gather.offset.*.2d_array.* dEQP-VK.glsl.texture_gather.offset_dynamic.*.2d_array.* dEQP-VK.glsl.texture_gather.offsets.*.2d_array.* Fixes: 854563f0f82 ("pco: fully switch over to common smp emission code") Signed-off-by: Nick Hamilton <[email protected]> Reviewed-by: Frank Binns <[email protected]> (cherry picked from commit b80a5f9b7db3894f7f232b0eedd35462475075ae) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 4799e79a by Georg Lehmann at 2026-04-29T17:53:11+02:00 nir: disable fp class analysis for 64bit transcendentals Some backends have terrible precision for these fp64 opcodes, so don't try to do anything clever. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15334 Fixes: 5a298f35606 ("nir: rewrite fp range analysis as a fp class analysis") Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric R. Smith <[email protected]> (cherry picked from commit 599a52174b407ac4ad377b4d6f0e95c62218cdff) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - ab91484f by Samuel Pitoiset at 2026-04-29T17:53:11+02:00 vulkan: add missing VkMemoryRangeBarriersInfoKHR support This has been introduced by VK_KHR_device_address_commands and we missed it completely. Backport-to: 26.1 Signed-off-by: Samuel Pitoiset <[email protected]> (cherry picked from commit ce60e18bce1a7564a8c8052d6a336c743f594270) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 94c81f2f by Samuel Pitoiset at 2026-04-29T17:53:11+02:00 radv: add missing VkMemoryRangeBarriersInfoKHR from DAC This is used to declare barrier dependencies for an addr range (because no VkBuffer with DAC). This fixes new dEQP-VK.api.device_address.misc.memory_range_barrier. Fixes: a97c889a7b5 ("radv: implement VK_KHR_device_address_commands") Signed-off-by: Samuel Pitoiset <[email protected]> (cherry picked from commit d1a428606e0f0867648c8187bc16f6e7d73e3737) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 7be90ef0 by Tapani Pälli at 2026-04-29T17:53:11+02:00 anv: do not use resource barrier with split barriers Fixes failing CTS tests using asymmetric and non-asymmetric (regular) split barriers. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15310 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit bdaf8b6b39f39a04a332c6d89af33be0e7858256) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 46a5ef37 by Georg Lehmann at 2026-04-29T17:53:11+02:00 intel/nir_opt_peephole_ffma: fix fp_math_ctlr for modifiers If abs/neg don't preserve nan/inf/sz, the whole expressions won't. Fixes: 1b0808adf3d ("intel/nir: Make ffma peephole optimization preserve fp_fast_math flags") Reviewed-by: Alyssa Rosenzweig <[email protected]> (cherry picked from commit 26ec32dada30211d88f7fc73bc0616cef82a68de) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 52b8d7fe by Alyssa Rosenzweig at 2026-04-29T17:53:11+02:00 nir/opt_reassociate: fix exactness bug For an inexact-associative operation (fadd or fmul), can_reassociate ensures the root of the chain is inexact to allow reassociating. However, build_chain just checks for opcodes to match up after, although we do sum up exactness across the chain. Although an Effort Was Made, it still seems incorrect to reassociate %3 = fadd! %0, %1 %4 = fadd %3, %2 to instead be (ex.) %3 = fadd! %0, %2 %4 = fadd! %3, %1 Closes: #14418 Fixes: e0b0f7e73c8 ("nir: add ALU reassocation pass") Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 0c49738211fe86e6a7b342bd85152389412f8e47) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 160d5c86 by Olivia Lee at 2026-04-29T17:53:11+02:00 pan/bi: fix memory access alignment Memory accesses need to be aligned up to the next power of two of the full access size. Component count and bit-size don't matter to the hardware, only the total size. shader-db results are pretty much what you would expect, there are a few shaders that have increased LS instructions as a result of splitting accesses to satisfy alignment requirements that were previously ignored. The one surprising thing is that there are several shaders that have reduced uniform usage. Looking at some of these individually, what happened is that splitting UBO loads early allowed the compiler to eliminate loads from unused ranges of the access. total instrs in shared programs: 719166 -> 719174 (<.01%) instrs in affected programs: 2355 -> 2363 (0.34%) helped: 4 HURT: 6 helped stats (abs) min: 1.0 max: 9.0 x̄: 3.00 x̃: 1 helped stats (rel) min: 0.36% max: 6.52% x̄: 1.99% x̃: 0.54% HURT stats (abs) min: 1.0 max: 4.0 x̄: 3.33 x̃: 4 HURT stats (rel) min: 0.65% max: 2.13% x̄: 1.38% x̃: 1.48% 95% mean confidence interval for instrs value: -2.14 3.74 95% mean confidence interval for instrs %-change: -1.76% 1.82% Inconclusive result (value mean confidence interval includes 0). total cycles in shared programs: 30210.83 -> 30218.81 (0.03%) cycles in affected programs: 50 -> 57.99 (15.97%) helped: 2 HURT: 6 helped stats (abs) min: 0.0078129999999999589 max: 0.070312000000000041 x̄: 0.04 x̃: 0 helped stats (rel) min: 1.10% max: 10.23% x̄: 5.66% x̃: 5.66% HURT stats (abs) min: 0.03125 max: 5.0 x̄: 1.34 x̃: 1 HURT stats (rel) min: 2.38% max: 25.00% x̄: 13.05% x̃: 14.26% 95% mean confidence interval for cycles value: -0.42 2.41 95% mean confidence interval for cycles %-change: -1.74% 18.49% Inconclusive result (value mean confidence interval includes 0). total cvt in shared programs: 2385.91 -> 2385.91 (<.01%) cvt in affected programs: 11.14 -> 11.14 (<.01%) helped: 5 HURT: 4 helped stats (abs) min: 0.0078119999999999301 max: 0.070312000000000041 x̄: 0.02 x̃: 0 helped stats (rel) min: 0.27% max: 10.23% x̄: 2.61% x̃: 0.82% HURT stats (abs) min: 0.01562600000000014 max: 0.03125 x̄: 0.03 x̃: 0 HURT stats (rel) min: 1.31% max: 2.75% x̄: 2.21% x̃: 2.40% 95% mean confidence interval for cvt value: -0.02 0.02 95% mean confidence interval for cvt %-change: -3.51% 2.58% Inconclusive result (value mean confidence interval includes 0). total ls in shared programs: 25871 -> 25879 (0.03%) ls in affected programs: 46 -> 54 (17.39%) helped: 0 HURT: 4 HURT stats (abs) min: 1.0 max: 5.0 x̄: 2.00 x̃: 1 HURT stats (rel) min: 10.00% max: 25.00% x̄: 18.38% x̃: 19.26% 95% mean confidence interval for ls value: -1.18 5.18 95% mean confidence interval for ls %-change: 8.46% 28.30% Inconclusive result (value mean confidence interval includes 0). total code size in shared programs: 6302848 -> 6302976 (<.01%) code size in affected programs: 1536 -> 1664 (8.33%) helped: 0 HURT: 1 total registers used in shared programs: 117324 -> 117329 (<.01%) registers used in affected programs: 45 -> 50 (11.11%) helped: 1 HURT: 2 helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1 helped stats (rel) min: 6.25% max: 6.25% x̄: 6.25% x̃: 6.25% HURT stats (abs) min: 2.0 max: 4.0 x̄: 3.00 x̃: 3 HURT stats (rel) min: 12.50% max: 30.77% x̄: 21.63% x̃: 21.63% total uniforms used in shared programs: 78538 -> 78274 (-0.34%) uniforms used in affected programs: 2688 -> 2424 (-9.82%) helped: 104 HURT: 4 helped stats (abs) min: 1.0 max: 18.0 x̄: 2.65 x̃: 2 helped stats (rel) min: 1.96% max: 54.55% x̄: 12.78% x̃: 11.11% HURT stats (abs) min: 1.0 max: 5.0 x̄: 3.00 x̃: 3 HURT stats (rel) min: 3.70% max: 16.13% x̄: 9.92% x̃: 9.92% 95% mean confidence interval for uniforms used value: -3.01 -1.88 95% mean confidence interval for uniforms used %-change: -14.15% -9.74% Uniforms used are helped. Total CPU time (seconds): 73.26 -> 74.48 (1.67%) Signed-off-by: Olivia Lee <[email protected]> Fixes: 2f2738dc9020 (pan/bi: Use nir_lower_mem_access_bit_sizes) Reviewed-by: Eric R. Smith <[email protected]> (cherry picked from commit 72e0eda2601beccf60ca4c0cde16e72b5a468050) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 8dbc8528 by Icenowy Zheng at 2026-04-29T17:53:11+02:00 pvr: skip emitting query program when copy result / reset with 0 queries When calling vkResetQueryPool() or vkCmdCopyQueryPoolResults() with a queryCount of 0, currently a query compute program with workgroup size 0*1*1 will be emited, which is ridiculous and will be rejected by some assertion in pvr_compute_generate_control_stream() . As the operation should be noop when queryCount is 0, the functions can and should just return in such cases. Fixes: 0aa9f32b95e6 ("pvr: Implement vkCmdResetQueryPool API.") Fixes: b6e8e1cf372f ("pvr: Implement vkCmdCopyQueryPoolResults API.") Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Nick Hamilton <[email protected]> (cherry picked from commit 01ba4867fa277628f53f03bfb140a89e030e572d) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 54650350 by Luigi Santivetti at 2026-04-29T17:53:11+02:00 pvr: add missing multi-arch support for pipeline exec and stats Entry points must be wrapped in the PVR_PER_ARCH macro else there will be multiple definitions of the same symbol. Fixes: dfddb3fe ("pvr: Add support for VK_KHR_pipeline_executable_properties") Signed-off-by: Luigi Santivetti <[email protected]> Reviewed-by: Frank Binns <[email protected]> (cherry picked from commit 120bd20e494c5d734dccf7643913ee5cfa997293) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 23633c2a by Benjamin Cheng at 2026-04-29T17:53:11+02:00 radv/wsi: Re-use transfer queue if it exists This avoids writing past the end of pdev->vk_queue_to_radv if all the queue families are available. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/14834 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 656b3814c28e514ef77379dac734890387c4761a) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 19ee4f8d by Job Noorman at 2026-04-29T17:53:11+02:00 ir3/shared_ra: fix live-out reload after src reload When reloading live-out values along loop back-edges, we make sure to reuse the original register. However, we failed to detect cases where the spilled value got reloaded earlier for a src in a different register. Fix this by reloading the value again in the original register. Fixes a RA validation failure in Windrose. Signed-off-by: Job Noorman <[email protected]> Fixes: fa22b0901af ("ir3/ra: Add specialized shared register RA/spilling") (cherry picked from commit aaf4d77f432f59902b53939bf0aee6f2121bbb02) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268> - - - - - 5112dfea by Eric Engestrom at 2026-04-29T21:01:34+02:00 VERSION: bump for 26.1.0-rc3 - - - - - 70 changed files: - .pick_status.json - VERSION - src/amd/common/ac_cmdbuf_cp.c - src/amd/common/nir/ac_nir_helpers.h - src/amd/common/nir/ac_nir_prerast_utils.c - src/amd/compiler/instruction_selection/aco_select_vs_prolog.cpp - src/amd/vulkan/radv_cmd_buffer.c - src/amd/vulkan/radv_cp_dma.c - src/amd/vulkan/radv_formats.c - src/amd/vulkan/radv_instance.c - src/amd/vulkan/radv_instance.h - src/amd/vulkan/radv_perfcounter.c - src/amd/vulkan/radv_video_enc.c - src/amd/vulkan/radv_wsi.c - src/compiler/nir/nir.h - src/compiler/nir/nir_intrinsics.py - src/compiler/nir/nir_opt_reassociate.c - src/compiler/nir/nir_range_analysis.c - src/freedreno/drm/virtio/virtio_pipe.c - src/freedreno/ir3/ir3_shared_ra.c - src/freedreno/vulkan/tu_knl_drm_virtio.cc - src/gallium/drivers/crocus/crocus_program.c - src/gallium/drivers/d3d12/d3d12_video_enc.cpp - src/gallium/drivers/d3d12/d3d12_video_enc.h - src/gallium/drivers/nouveau/nv50/nv50_tex.c - src/gallium/drivers/nouveau/nvc0/nvc0_tex.c - src/gallium/drivers/r300/ci/r300-rs740-fails.txt - src/gallium/drivers/r300/ci/r300-rs740-flakes.txt - src/gallium/drivers/r300/ci/r300-rv380-fails.txt - src/gallium/drivers/r300/ci/r300-rv380-flakes.txt - src/gallium/drivers/r300/ci/r300-rv410-fails.txt - src/gallium/drivers/r300/ci/r300-rv410-flakes.txt - src/gallium/drivers/r300/ci/r300-rv530-fails.txt - src/gallium/drivers/r300/ci/r300-rv530-flakes.txt - src/gallium/drivers/r300/r300_blit.c - src/gallium/drivers/r300/r300_context.h - src/gallium/drivers/r300/r300_emit.c - src/gallium/drivers/r300/r300_state.c - src/gallium/drivers/r300/r300_state_derived.c - src/gallium/drivers/radeonsi/si_cp_dma.c - src/gallium/drivers/radeonsi/si_shader.c - src/gallium/drivers/zink/ci/gitlab-ci.yml - − src/gallium/drivers/zink/ci/zink-radv-cezanne-fails.txt - − src/gallium/drivers/zink/ci/zink-radv-cezanne-flakes.txt - − src/gallium/drivers/zink/ci/zink-radv-cezanne-skips.txt - − src/gallium/drivers/zink/ci/zink-radv-cezanne-validation-settings.txt - src/gallium/drivers/zink/zink_bo.c - src/gallium/frontends/va/picture_hevc.c - src/gallium/frontends/wgl/stw_context.c - src/gallium/frontends/wgl/stw_framebuffer.c - src/imagination/pco/pco_internal.h - src/imagination/pco/pco_nir.c - src/imagination/pco/pco_nir_tex.c - src/imagination/pco/pco_trans_nir.c - src/imagination/vulkan/pvr_arch_cmd_query.c - src/imagination/vulkan/pvr_arch_pipeline.c - src/imagination/vulkan/pvr_physical_device.c - src/intel/compiler/intel_nir_opt_peephole_ffma.c - src/intel/vulkan/anv_instance.c - src/intel/vulkan/anv_physical_device.c - src/intel/vulkan/anv_private.h - src/intel/vulkan/genX_cmd_buffer.c - src/panfrost/compiler/bifrost/bi_repair_ssa.c - src/panfrost/compiler/bifrost/bifrost_nir.c - src/panfrost/vulkan/csf/panvk_vX_cmd_draw.c - src/panfrost/vulkan/panvk_instance.h - src/util/00-mesa-defaults.conf - src/util/00-radv-defaults.conf - src/util/driconf.h - src/vulkan/runtime/vk_synchronization.c The diff was not included because it is too large. View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/9445e5d0a6c2032882f1cd479b7fb78df6f5f0eb...5112dfea2243437b31b640d471216f489ffa8b10 -- View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/9445e5d0a6c2032882f1cd479b7fb78df6f5f0eb...5112dfea2243437b31b640d471216f489ffa8b10 You're receiving this email because of your account on salsa.debian.org. Manage all notifications: https://salsa.debian.org/-/profile/notifications | Help: https://salsa.debian.org/help
