Makefile.am | 11 README.ati | 828 ----- README.ati.sgml | 648 ---- README.r128 | 160 - README.r128.sgml | 138 configure.ac | 83 man/Makefile.am | 5 man/r128.man | 156 - man/radeon.man | 54 src/AtomBios/CD_Operations.c | 9 src/AtomBios/Decoder.c | 9 src/AtomBios/includes/CD_Common_Types.h | 8 src/AtomBios/includes/ObjectID.h | 928 +++--- src/AtomBios/includes/atombios.h | 50 src/Makefile.am | 91 src/ati.c | 6 src/ati.h | 3 src/ati_pciids_gen.h | 30 src/atiadjust.c | 134 src/atiadjust.h | 31 src/atiaudio.c | 50 src/atiaudio.h | 51 src/atibank.c | 114 src/atibank.h | 44 src/atibus.c | 123 src/atibus.h | 49 src/atichip.c | 271 - src/atichip.h | 94 src/aticlock.c | 443 --- src/aticlock.h | 62 src/aticonfig.c | 506 --- src/aticonsole.c | 816 ----- src/aticonsole.h | 43 src/aticrtc.h | 42 src/aticursor.h | 42 src/atidac.c | 462 --- src/atidac.h | 99 src/atidecoder.c | 50 src/atidecoder.h | 51 src/atidga.c | 483 --- src/atidga.h | 36 src/atidri.c | 1640 ----------- src/atidri.h | 49 src/atidripriv.h | 57 src/atidsp.c | 302 -- src/atidsp.h | 35 src/atii2c.c | 399 -- src/atii2c.h | 48 src/atiload.c | 98 src/atiload.h | 32 src/atilock.c | 537 --- src/atilock.h | 31 src/atimach64.c | 1341 --------- src/atimach64.h | 36 src/atimach64accel.c | 1068 ------- src/atimach64accel.h | 42 src/atimach64cursor.c | 426 --- src/atimach64exa.c | 696 ---- src/atimach64i2c.c | 469 --- src/atimach64i2c.h | 32 src/atimach64io.c | 103 src/atimach64io.h | 421 --- src/atimach64probe.c | 289 -- src/atimach64probe.h | 32 src/atimach64render.c | 898 ------ src/atimach64version.h | 59 src/atimach64xv.c | 1686 ------------ src/atimisc.c | 78 src/atimode.c | 1084 ------- src/atimode.h | 35 src/atimodule.c | 2 src/atioption.h | 98 src/atipreinit.c | 2509 ----------------- src/atipreinit.h | 30 src/atiprint.c | 784 ----- src/atiprint.h | 34 src/atipriv.h | 30 src/atiprobe.c | 475 --- src/atiprobe.h | 30 src/atiregs.h | 2882 -------------------- src/atirgb514.c | 283 -- src/atirgb514.h | 35 src/atiscreen.c | 692 ---- src/atiscreen.h | 31 src/atistruct.h | 529 --- src/atituner.c | 177 - src/atituner.h | 69 src/atiutil.c | 117 src/atiutil.h | 67 src/ativalid.c | 161 - src/ativalid.h | 30 src/ativga.c | 195 - src/ativga.h | 40 src/ativgaio.c | 49 src/ativgaio.h | 56 src/atividmem.c | 483 --- src/atividmem.h | 73 src/atiwonder.c | 159 - src/atiwonder.h | 38 src/atiwonderio.c | 66 src/atiwonderio.h | 46 src/atixv.h | 34 src/atombios_crtc.c | 206 - src/atombios_output.c | 499 +++ src/generic_bus.h | 9 src/legacy_crtc.c | 194 - src/legacy_output.c | 209 + src/mach64_common.h | 130 src/mach64_dri.h | 125 src/mach64_sarea.h | 162 - src/pcidb/ati_pciids.csv | 50 src/r128.h | 606 ---- src/r128_accel.c | 1880 ------------- src/r128_common.h | 169 - src/r128_cursor.c | 311 -- src/r128_dga.c | 402 -- src/r128_dri.c | 1499 ---------- src/r128_dri.h | 100 src/r128_dripriv.h | 57 src/r128_driver.c | 4463 -------------------------------- src/r128_misc.c | 79 src/r128_probe.c | 378 -- src/r128_probe.h | 73 src/r128_reg.h | 1533 ---------- src/r128_sarea.h | 194 - src/r128_version.h | 59 src/r128_video.c | 1028 ------- src/radeon.h | 623 ++-- src/radeon_accel.c | 164 - src/radeon_accelfuncs.c | 19 src/radeon_atombios.c | 1284 ++------- src/radeon_atombios.h | 13 src/radeon_atomwrapper.c | 2 src/radeon_bios.c | 411 ++ src/radeon_chipinfo_gen.h | 38 src/radeon_chipset_gen.h | 42 src/radeon_common.h | 2 src/radeon_commonfuncs.c | 671 +++- src/radeon_crtc.c | 228 + src/radeon_cursor.c | 53 src/radeon_dga.c | 10 src/radeon_dri.c | 37 src/radeon_dri.h | 2 src/radeon_driver.c | 1112 +++++-- src/radeon_exa.c | 52 src/radeon_exa_funcs.c | 66 src/radeon_exa_render.c | 1376 ++++++++- src/radeon_macros.h | 20 src/radeon_mm_i2c.c | 22 src/radeon_output.c | 593 ++-- src/radeon_pci_chipset_gen.h | 30 src/radeon_pci_device_match_gen.h | 30 src/radeon_probe.c | 2 src/radeon_probe.h | 503 +-- src/radeon_reg.h | 1272 +++++++++ src/radeon_render.c | 73 src/radeon_textured_video.c | 401 ++ src/radeon_textured_videofuncs.c | 647 ++++ src/radeon_tv.c | 100 src/radeon_video.c | 342 +- src/radeon_video.h | 70 src/radeon_vip.c | 42 src/theatre.c | 310 +- src/theatre.h | 116 src/theatre200.c | 356 +- src/theatre_detect.c | 17 src/theatre_detect.h | 4 src/theatre_reg.h | 306 +- 168 files changed, 9468 insertions(+), 46048 deletions(-)
New commits: commit 67a6ac0001bc9d062aa426384a11a41fa7a1c09a Author: Alex Deucher <[EMAIL PROTECTED]> Date: Tue Jun 24 21:06:37 2008 -0400 bump for rc release diff --git a/configure.ac b/configure.ac index 7418558..beafb7e 100644 --- a/configure.ac +++ b/configure.ac @@ -22,7 +22,7 @@ AC_PREREQ(2.57) AC_INIT([xf86-video-ati], - 6.8.191, + 6.8.192, [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], xf86-video-ati) commit bd68507d2d66e03d8bcde5f6e7ea9b2dbfe8b8a0 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Tue Jun 24 20:59:58 2008 -0400 RADEON: warning fix diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 17ae8c4..3df61a7 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -636,7 +636,6 @@ void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) { int mask; - ScrnInfoPtr pScrn = crtc->scrn; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); unsigned char *RADEONMMIO = pRADEONEnt->MMIO; commit 8e534d69c9b19fc085f7c5ca9e18f5ea04f6fc12 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Tue Jun 24 20:08:35 2008 -0400 RADEON: cleanups - fix some warnings - RS400 and RS480 are separate families now (update default tmds and dac2 tables) diff --git a/src/radeon_output.c b/src/radeon_output.c index 9198920..7b89d66 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -144,6 +144,7 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ + {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */ }; static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = @@ -166,6 +167,7 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = 0x01080000, /* r420 */ 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */ 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ + 0x00780000, /* rs480 */ /* FIXME: just values from rv380 used... */ }; @@ -584,7 +586,6 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, static void radeon_mode_prepare(xf86OutputPtr output) { - RADEONInfoPtr info = RADEONPTR(output->scrn); xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); int o; @@ -624,7 +625,6 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, static void radeon_mode_commit(xf86OutputPtr output) { - RADEONInfoPtr info = RADEONPTR(output->scrn); xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); int o; commit e78e8a21b4040cd7f1983c241c860d9209398396 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Tue Jun 24 19:53:28 2008 -0400 IGP: attempt to fix VGA on IGP chips VGA has never worked on some IGP chips. While the chip only has one DAC, it appears to use a mix of Primary DAC and TVDAC controls. See bug 15708 diff --git a/src/legacy_output.c b/src/legacy_output.c index 4df81ab..9c9ebb9 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c @@ -727,6 +727,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; } tv_dac_change = 1; + /* IGP chips seem to use a mix of Primary and TVDAC controls */ + if (info->IsIGP) { + tmp = INREG(RADEON_CRTC_EXT_CNTL); + tmp |= RADEON_CRTC_CRT_ON; + OUTREG(RADEON_CRTC_EXT_CNTL, tmp); + save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; + RADEONDacPowerSet(pScrn, bEnable, TRUE); + } } } else if (radeon_output->MonType == MT_DFP) { if (radeon_output->TMDSType == TMDS_INT) { @@ -807,6 +815,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; } } + /* IGP chips seem to use a mix of Primary and TVDAC controls */ + if (info->IsIGP) { + tmp = INREG(RADEON_CRTC_EXT_CNTL); + tmp &= ~RADEON_CRTC_CRT_ON; + OUTREG(RADEON_CRTC_EXT_CNTL, tmp); + save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; + RADEONDacPowerSet(pScrn, bEnable, TRUE); + } } } else if (radeon_output->MonType == MT_DFP) { if (radeon_output->TMDSType == TMDS_INT) { @@ -1367,6 +1383,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, { Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE; RADEONOutputPrivatePtr radeon_output = output->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); if (crtc_num == 0) RADEONInitRMXRegisters(output, save, mode); @@ -1376,6 +1393,9 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, RADEONInitDACRegisters(output, save, mode, IsPrimary); } else { RADEONInitDAC2Registers(output, save, mode, IsPrimary); + /* IGP chips seem to use a mix of primary and TVDAC controls */ + if (info->IsIGP) + RADEONInitDACRegisters(output, save, mode, IsPrimary); } } else if (radeon_output->MonType == MT_LCD) { RADEONInitLVDSRegisters(output, save, mode, IsPrimary); commit faa4b4b8dbe9b8a452cfa60d53874350bb04e0cb Author: Jiří Paleček <[EMAIL PROTECTED]> Date: Tue Jun 24 19:20:50 2008 -0400 RADEON: remove extraneous line from new pll code diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 8f2d4fc..c63b650 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -144,7 +144,6 @@ RADEONComputePLL(RADEONPLLPtr pll, if (flags & RADEON_PLL_USE_REF_DIV) min_ref_div = max_ref_div = pll->reference_div; else { - max_ref_div = 2*max_ref_div - min_ref_div; while (min_ref_div < max_ref_div-1) { uint32_t mid=(min_ref_div+max_ref_div)/2; uint32_t pll_in = pll->reference_freq / mid; commit 72feaa37ea07620f5f2ead438dbc72a1c8883cd3 Author: Jiří Paleček <[EMAIL PROTECTED]> Date: Mon Jun 23 15:53:58 2008 -0400 RADEON: PLL tweaks Patch from Jiří Paleček (see debian bug 465864) with some tweaks by me. - abort rather than programming bad dividers if no pll dividers can be found - improve the pll selection algorithm - in general, prefer lower ref dividers I've tested this patch on a wide variety of chips (r1xx-r6xx) and clocks. diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index b5b7ca8..363addf 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -185,8 +185,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) if (IS_AVIVO_VARIANT) { uint32_t temp; - if (IS_DCE3_VARIANT) - pll_flags |= RADEON_PLL_DCE3; + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); sclock = temp; diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 747bc6e..17ae8c4 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -1730,7 +1730,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, RADEONInfoPtr info = RADEONPTR(pScrn); int i = 0; double dot_clock = 0; - int pll_flags = RADEON_PLL_LEGACY; + int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; Bool update_tv_routing = FALSE; Bool tilingChanged = FALSE; diff --git a/src/radeon.h b/src/radeon.h index cdd84ea..4f77c3b 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -220,7 +220,7 @@ typedef struct { #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) #define RADEON_PLL_LEGACY (1 << 3) -#define RADEON_PLL_DCE3 (1 << 4) +#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) typedef struct { uint16_t reference_freq; diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 9eb36ed..8f2d4fc 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -132,7 +132,7 @@ RADEONComputePLL(RADEONPLLPtr pll, uint32_t best_post_div = 1; uint32_t best_ref_div = 1; uint32_t best_feedback_div = 1; - uint32_t best_freq = 1; + uint32_t best_freq = -1; uint32_t best_error = 0xffffffff; uint32_t best_vco_diff = 1; uint32_t post_div; @@ -143,10 +143,21 @@ RADEONComputePLL(RADEONPLLPtr pll, if (flags & RADEON_PLL_USE_REF_DIV) min_ref_div = max_ref_div = pll->reference_div; + else { + max_ref_div = 2*max_ref_div - min_ref_div; + while (min_ref_div < max_ref_div-1) { + uint32_t mid=(min_ref_div+max_ref_div)/2; + uint32_t pll_in = pll->reference_freq / mid; + if (pll_in < pll->pll_in_min) + max_ref_div = mid; + else if (pll_in > pll->pll_in_max) + min_ref_div = mid; + else break; + } + } for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { uint32_t ref_div; - uint32_t vco = (freq / 10000) * post_div; if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) continue; @@ -161,45 +172,71 @@ RADEONComputePLL(RADEONPLLPtr pll, continue; } - if (vco < pll->pll_out_min || vco > pll->pll_out_max) - continue; - for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { uint32_t feedback_div, current_freq, error, vco_diff; uint32_t pll_in = pll->reference_freq / ref_div; + uint32_t min_feed_div = pll->min_feedback_div; + uint32_t max_feed_div = pll->max_feedback_div+1; if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) continue; - feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div, - pll->reference_freq * 10000); + while (min_feed_div < max_feed_div) { + uint32_t vco; - if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) - continue; + feedback_div = (min_feed_div+max_feed_div)/2; + + vco = RADEONDiv((CARD64)pll->reference_freq * feedback_div, + ref_div); - current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, - ref_div * post_div); - - error = abs(current_freq - freq); - vco_diff = abs(vco - best_vco); - - if ((best_vco == 0 && error < best_error) || - (ref_div == pll->reference_div) || - (best_vco != 0 && - (error < best_error - 100 || - (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { - best_post_div = post_div; - best_ref_div = ref_div; - best_feedback_div = feedback_div; - best_freq = current_freq; - best_error = error; - best_vco_diff = vco_diff; + if (vco < pll->pll_out_min) { + min_feed_div = feedback_div+1; + continue; + } else if(vco > pll->pll_out_max) { + max_feed_div = feedback_div; + continue; + } + + current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, + ref_div * post_div); + + error = abs(current_freq - freq); + vco_diff = abs(vco - best_vco); + + if ((best_vco == 0 && error < best_error) || + (best_vco != 0 && + (error < best_error - 100 || + (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { + best_post_div = post_div; + best_ref_div = ref_div; + best_feedback_div = feedback_div; + best_freq = current_freq; + best_error = error; + best_vco_diff = vco_diff; + } else if (current_freq == freq) { + if (best_freq == -1) { + best_post_div = post_div; + best_ref_div = ref_div; + best_feedback_div = feedback_div; + best_freq = current_freq; + best_error = error; + best_vco_diff = vco_diff; + } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) { + best_post_div = post_div; + best_ref_div = ref_div; + best_feedback_div = feedback_div; + best_freq = current_freq; + best_error = error; + best_vco_diff = vco_diff; + } + } + + if (current_freq < freq) + min_feed_div = feedback_div+1; + else + max_feed_div = feedback_div; } } - if (!(flags & RADEON_PLL_DCE3)) { - if (best_freq == freq) - break; - } } ErrorF("best_freq: %u\n", (unsigned int)best_freq); @@ -207,6 +244,8 @@ RADEONComputePLL(RADEONPLLPtr pll, ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); + if (best_freq == -1) + FatalError("Couldn't find valid PLL dividers\n"); *chosen_dot_clock_freq = best_freq / 10000; *chosen_feedback_div = best_feedback_div; *chosen_reference_div = best_ref_div; commit 9c2f909ea437a63a408d2398ecabe0b378dbb982 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Mon Jun 23 10:38:15 2008 -0400 RADEON: adjust randr crtc/output prepare/commit ordering This fixes some occasional mode change problems with multiple heads active. It seems radeons generally like to turn on the whole output/crtc setup in one shot. diff --git a/src/radeon.h b/src/radeon.h index 94611a8..cdd84ea 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -880,6 +880,7 @@ extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); /* radeon_crtc.c */ +extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index b1e978c..9eb36ed 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -59,7 +59,7 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, int x, int y); extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); -static void +void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) { RADEONInfoPtr info = RADEONPTR(crtc->scrn); @@ -110,7 +110,6 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc) if (radeon_crtc->enabled) crtc->funcs->hide_cursor(crtc); - radeon_crtc_dpms(crtc, DPMSModeOff); } static uint32_t RADEONDiv(CARD64 n, uint32_t d) @@ -232,25 +231,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, static void radeon_crtc_mode_commit(xf86CrtcPtr crtc) { - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - xf86CrtcPtr other; - if (radeon_crtc->crtc_id == 1) - other = pRADEONEnt->pCrtc[0]; - else - other = pRADEONEnt->pCrtc[1]; - if (other->enabled) - radeon_crtc_dpms(other, DPMSModeOn); - } - - radeon_crtc_dpms(crtc, DPMSModeOn); - if (crtc->scrn->pScreen != NULL) xf86_reload_cursors(crtc->scrn->pScreen); - } void diff --git a/src/radeon_output.c b/src/radeon_output.c index 1f289cb..9198920 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -584,8 +584,27 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, static void radeon_mode_prepare(xf86OutputPtr output) { + RADEONInfoPtr info = RADEONPTR(output->scrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); + int o; + + for (o = 0; o < config->num_output; o++) { + xf86OutputPtr loop_output = config->output[o]; + if (loop_output == output) + continue; + else if (loop_output->crtc) { + xf86CrtcPtr other_crtc = loop_output->crtc; + if (other_crtc->enabled) { + radeon_dpms(loop_output, DPMSModeOff); + radeon_crtc_dpms(other_crtc, DPMSModeOff); + } + } + } + radeon_bios_output_lock(output, TRUE); radeon_dpms(output, DPMSModeOff); + radeon_crtc_dpms(output->crtc, DPMSModeOff); + } static void @@ -605,7 +624,25 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, static void radeon_mode_commit(xf86OutputPtr output) { + RADEONInfoPtr info = RADEONPTR(output->scrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); + int o; + + for (o = 0; o < config->num_output; o++) { + xf86OutputPtr loop_output = config->output[o]; + if (loop_output == output) + continue; + else if (loop_output->crtc) { + xf86CrtcPtr other_crtc = loop_output->crtc; + if (other_crtc->enabled) { + radeon_dpms(loop_output, DPMSModeOn); + radeon_crtc_dpms(other_crtc, DPMSModeOn); + } + } + } + radeon_dpms(output, DPMSModeOn); + radeon_crtc_dpms(output->crtc, DPMSModeOn); radeon_bios_output_lock(output, FALSE); } commit aea9bf75cf0774afd3e65fcf3fd3851f5fb21ca3 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Sat Jun 21 10:57:05 2008 -0400 0x1002 0x5657 is actually RV410 See bug 14289 com_bios_scratch.diff diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h index eee1d60..a740df8 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h @@ -173,6 +173,7 @@ #define PCI_CHIP_RV410_564F 0x564F #define PCI_CHIP_RV410_5652 0x5652 #define PCI_CHIP_RV410_5653 0x5653 +#define PCI_CHIP_RV410_5657 0x5657 #define PCI_CHIP_MACH64VT 0x5654 #define PCI_CHIP_MACH64VU 0x5655 #define PCI_CHIP_MACH64VV 0x5656 @@ -195,7 +196,6 @@ #define PCI_CHIP_RV370_5B60 0x5B60 #define PCI_CHIP_RV370_5B62 0x5B62 #define PCI_CHIP_RV370_5B63 0x5B63 -#define PCI_CHIP_RV370_5657 0x5657 #define PCI_CHIP_RV370_5B64 0x5B64 #define PCI_CHIP_RV370_5B65 0x5B65 #define PCI_CHIP_RV280_5C61 0x5C61 diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv index 9e19275..1f6fa82 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv @@ -174,6 +174,7 @@ "0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" "0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" "0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" +"0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX 5657 (PCIE)" "0x5654","MACH64VT","MACH64",,,,,, "0x5655","MACH64VU","MACH64",,,,,, "0x5656","MACH64VV","MACH64",,,,,, @@ -196,7 +197,6 @@ "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" -"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)" "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h index fbcebae..ed3174a 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h @@ -96,6 +96,7 @@ RADEONCardInfo RADEONCards[] = { { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, + { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, @@ -115,7 +116,6 @@ RADEONCardInfo RADEONCards[] = { { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h index b60e7e8..d1761d2 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h @@ -96,6 +96,7 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, + { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" }, { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, @@ -115,7 +116,6 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, - { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" }, { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h index 7e4cb17..39adb5e 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h @@ -96,6 +96,7 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA }, { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, @@ -115,7 +116,6 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h index 72ff0d1..d81cbe3 100644 --- a/src/radeon_pci_device_match_gen.h +++ b/src/radeon_pci_device_match_gen.h @@ -96,6 +96,7 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ), @@ -115,7 +116,6 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ), commit 38ce8a984f96056b7345bcc06505ba27e0e6d5b4 Author: Dave Airlie <[EMAIL PROTECTED]> Date: Fri Jun 20 14:16:22 2008 +1000 legacy: use entity MMIO for dpms as this can crossover between zaphod infos diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 590a445..747bc6e 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -638,8 +638,8 @@ legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) int mask; ScrnInfoPtr pScrn = crtc->scrn; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; + RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); + unsigned char *RADEONMMIO = pRADEONEnt->MMIO; mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS); commit 1a7d9bc53512b0a5240176c949e6abf1ae2fb1fd Author: Dave Airlie <[EMAIL PROTECTED]> Date: Fri Jun 20 14:14:21 2008 +1000 atombios: use MMIO from the entity not the info diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index 314bc15..900e928 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -2047,8 +2047,8 @@ UINT32 CailReadATIRegister(VOID* CAIL, UINT32 idx) { ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = pRADEONEnt->MMIO; UINT32 ret; CAILFUNC(CAIL); @@ -2061,8 +2061,8 @@ VOID CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) { ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = pRADEONEnt->MMIO; CAILFUNC(CAIL); OUTREG(idx << 2,data); commit ef624b88903b1a87ef5b6388e18291f75776b93d Author: Alex Deucher <[EMAIL PROTECTED]> Date: Thu Jun 19 18:20:52 2008 -0400 RADEON: fix read past the end of an array diff --git a/src/radeon_output.c b/src/radeon_output.c index 72addef..1f289cb 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -74,12 +74,13 @@ const RADEONMonitorType MonTypeID[10] = { MT_DP }; -const char *TMDSTypeName[5] = { +const char *TMDSTypeName[6] = { "None", "Internal", "External", "LVTMA", - "DDIA" + "DDIA", + "UNIPHY" }; const char *DACTypeName[4] = { commit cfe814a481d8cf2005d738a0ca9782f1ed4177f5 Author: Dave Airlie <[EMAIL PROTECTED]> Date: Fri Jun 20 07:51:27 2008 +1000 r600: don't add fb offset here to make shadowfb work. discovered on irc with wpwrak. diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 2516590..f18ad99 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -224,8 +224,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; - return ((uint8_t *)info->FB + pScrn->fbOffset + - row * stride + offset); + return ((uint8_t *)info->FB + row * stride + offset); } static Bool RADEONCreateScreenResources (ScreenPtr pScreen) commit eed241553748125e902c44dcc8cf8e0605be071b Author: Alex Deucher <[EMAIL PROTECTED]> Date: Tue Jun 17 17:42:31 2008 -0400 radeon: X_ERROR -> X_WARNING for num gb pipes This just means your drm is old, not fatal or anything diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 5897c7e..d45e932 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -381,7 +381,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np, sizeof(np)) < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to determine num pipes from DRM, falling back to " "manual look-up!\n"); info->num_gb_pipes = 0; commit dd18caa4b2efc430eaae0c4362b65641f9bef440 Author: Dave Airlie <[EMAIL PROTECTED]> Date: Sat Jun 14 18:37:56 2008 +1000 Revert "ATOM: disable TV-out for now" This reverts commit effa245914823371e052cd9aa1143a02350891e7. diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index e24697b..314bc15 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -1787,13 +1787,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) continue; } #endif -#if 1 - if (i == ATOM_DEVICE_TV1_INDEX) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n"); - info->BiosConnector[i].valid = FALSE; - continue; - } -#endif info->BiosConnector[i].valid = TRUE; info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; commit b416e97a1f16ef700ba1aaca317dee82b7a3cf64 Author: Alex Deucher <[EMAIL PROTECTED]> Date: Fri Jun 13 02:21:31 2008 -0400 RADEON: man page updates diff --git a/man/radeon.man b/man/radeon.man index 1d14358..03622a0 100644 --- a/man/radeon.man +++ b/man/radeon.man @@ -52,11 +52,11 @@ Radeon 9100 IGP .B RS350 Radeon 9200 IGP .TP 12 -.B RS400 -Radeon XPRESS 200/200M IGP +.B RS400/RS480 +Radeon XPRESS 200(M)/1100 IGP .TP 12 .B RV280 -Radeon 9200PRO/9200/9200SE, M9+ +Radeon 9200PRO/9200/9200SE/9250, M9+ .TP 12 .B R300 Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1 @@ -68,9 +68,9 @@ Radeon 9800PRO/9800SE/9800, FireGL X2 Radeon 9800XT .TP 12 .B RV350 -Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 +Radeon 9600PRO/9600SE/9600/9550, M10/M11, FireGL T2 .TP 12 -.B RV360 +.B RV360 Radeon 9600XT .TP 12 .B RV370 @@ -91,8 +91,8 @@ Radeon X800, M28 PCIE .B R480/R481 Radeon X850 PCIE/AGP .TP 12 -.B RV515 -Radeon X1300/X1400/X1500 +.B RV505/RV515/RV516/RV550 +Radeon X1300/X1400/X1500/X2300 .TP 12 -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". 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