src/nouveau_channel.c | 7
src/nouveau_xv.c | 13
src/nv30_exa.c | 29 +
src/nv30_shaders.c | 126 ++-----
src/nv30_shaders.h | 2
src/nv30_xv_tex.c | 11
src/nv40_exa.c | 32 +
src/nv40_xv_tex.c | 11
src/nv_accel_common.c | 29 +
src/nv_bios.c | 869 +++++++++++++++++++++-----------------------------
src/nv_crtc.c | 526 +++++++++++++-----------------
src/nv_driver.c | 264 ++++++---------
src/nv_hw.c | 314 +++++++++---------
src/nv_output.c | 115 ++----
src/nv_proto.h | 26 -
src/nv_setup.c | 124 +++----
src/nv_type.h | 5
src/nvreg.h | 219 ++++++++----
18 files changed, 1326 insertions(+), 1396 deletions(-)
New commits:
commit cea05e14f94dcb842adbfcec515e17e9f5655089
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Sun Oct 26 03:51:36 2008 +0000
randr12: make colour-map setting less complex
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index c069b57..59db4be 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -1060,48 +1060,47 @@ static void nv_crtc_unlock(xf86CrtcPtr crtc)
{
}
+#define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
+
static void
nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
int size)
{
struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
- ScrnInfoPtr pScrn = crtc->scrn;
- NVPtr pNv = NVPTR(pScrn);
- NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
- int i, j;
+ NVPtr pNv = NVPTR(crtc->scrn);
+ struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
+ int i;
- switch (pScrn->depth) {
+ rgbs = (struct rgb *)pNv->ModeReg.crtc_reg[nv_crtc->head].DAC;
+
+ switch (crtc->scrn->depth) {
case 15:
/* R5G5B5 */
- /* We've got 5 bit (32 values) colors and 256 registers for
each color */
- for (i = 0; i < 32; i++)
- for (j = 0; j < 8; j++) {
- regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
- regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
- regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
- }
+ /* spread 5 bits per colour (32 colours) over 256 (per colour)
registers */
+ for (i = 0; i < 32; i++) {
+ rgbs[DEPTH_SHIFT(i, 5)].r = red[i] >> 8;
+ rgbs[DEPTH_SHIFT(i, 5)].g = green[i] >> 8;
+ rgbs[DEPTH_SHIFT(i, 5)].b = blue[i] >> 8;
+ }
break;
case 16:
/* R5G6B5 */
- /* First deal with the 5 bit colors */
- for (i = 0; i < 32; i++)
- for (j = 0; j < 8; j++) {
- regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
- regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
+ for (i = 0; i < 64; i++) {
+ /* set 64 regs for green's 6 bits of colour */
+ rgbs[DEPTH_SHIFT(i, 6)].g = green[i] >> 8;
+ if (i < 32) {
+ rgbs[DEPTH_SHIFT(i, 5)].r = red[i] >> 8;
+ rgbs[DEPTH_SHIFT(i, 5)].b = blue[i] >> 8;
}
- /* Now deal with the 6 bit color */
- for (i = 0; i < 64; i++)
- for (j = 0; j < 4; j++)
- regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
+ }
break;
default:
/* R8G8B8 */
for (i = 0; i < 256; i++) {
- regp->DAC[i * 3] = red[i] >> 8;
- regp->DAC[(i * 3) + 1] = green[i] >> 8;
- regp->DAC[(i * 3) + 2] = blue[i] >> 8;
+ rgbs[i].r = red[i] >> 8;
+ rgbs[i].g = green[i] >> 8;
+ rgbs[i].b = blue[i] >> 8;
}
- break;
}
nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
commit 0e4b01a5e06d8b5323c010ce89723369f17b10b2
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Sat Oct 25 02:11:37 2008 +0100
randr12: convenience functions for vga crtc state access
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 10ee1d6..c069b57 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -70,6 +70,19 @@ static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t
reg, uint32_t val)
NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
}
+static void crtc_rd_cio_state(xf86CrtcPtr crtc, NVCrtcRegPtr crtcstate, int
index)
+{
+ crtcstate->CRTC[index] = NVReadVgaCrtc(NVPTR(crtc->scrn),
+ to_nouveau_crtc(crtc)->head,
+ index);
+}
+
+static void crtc_wr_cio_state(xf86CrtcPtr crtc, NVCrtcRegPtr crtcstate, int
index)
+{
+ NVWriteVgaCrtc(NVPTR(crtc->scrn), to_nouveau_crtc(crtc)->head, index,
+ crtcstate->CRTC[index]);
+}
+
/* Even though they are not yet used, i'm adding some notes about some of the
0x4000 regs */
/* They are only valid for NV4x, appearantly reordered for NV5x */
/* gpu pll: 0x4000 + 0x4004
@@ -168,24 +181,24 @@ static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
NVPtr pNv = NVPTR(crtc->scrn);
struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
uint32_t cursor_start;
- uint8_t *CRTC = pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC;
+ NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
if (pNv->Architecture == NV_ARCH_04)
cursor_start = 0x5E00 << 2;
else
cursor_start = nv_crtc->head ? pNv->Cursor2->offset :
pNv->Cursor->offset;
- CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
+ regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
if (pNv->Architecture != NV_ARCH_04)
- CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
- CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
+ regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
+ regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
if (crtc->mode.Flags & V_DBLSCAN)
- CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
- CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
+ regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
+ regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX,
CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX,
CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
if (pNv->Architecture == NV_ARCH_40)
nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
}
@@ -1323,7 +1336,7 @@ static void nv_crtc_load_state_vga(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
for (i = 0; i < 25; i++)
- NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
+ crtc_wr_cio_state(crtc, regp, i);
for (i = 0; i < 9; i++)
NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
@@ -1361,7 +1374,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1),
pNv->VRAMPhysicalSize - 1);
nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21,
regp->CRTC[NV_CIO_CRE_21]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_21);
NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG,
regp->cursorConfig);
NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
@@ -1382,44 +1395,44 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX,
regp->CRTC[NV_CIO_CRE_RPC0_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX,
regp->CRTC[NV_CIO_CRE_RPC1_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX,
regp->CRTC[NV_CIO_CRE_LSR_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX,
regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX,
regp->CRTC[NV_CIO_CRE_LCD__INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX,
regp->CRTC[NV_CIO_CRE_HEB__INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX,
regp->CRTC[NV_CIO_CRE_ENH_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX,
regp->CRTC[NV_CIO_CRE_FF_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX,
regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC1_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_LSR_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_LCD__INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HEB__INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_ENH_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
if (pNv->Architecture >= NV_ARCH_30)
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47,
regp->CRTC[NV_CIO_CRE_47]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX,
regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX,
regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
if (pNv->Architecture == NV_ARCH_40)
nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX,
regp->CRTC[NV_CIO_CRE_ILACE__INDEX]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX,
regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX,
regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH4__INDEX);
if (pNv->Architecture >= NV_ARCH_10) {
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX,
regp->CRTC[NV_CIO_CRE_EBR_INDEX]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB,
regp->CRTC[NV_CIO_CRE_CSB]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B,
regp->CRTC[NV_CIO_CRE_4B]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52,
regp->CRTC[NV_CIO_CRE_52]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_EBR_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_4B);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_52);
}
/* NV11 and NV20 stop at 0x52. */
if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53,
regp->CRTC[NV_CIO_CRE_53]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54,
regp->CRTC[NV_CIO_CRE_54]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_53);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_54);
for (i = 0; i < 0x10; i++)
NVWriteVgaCrtc5758(pNv, nv_crtc->head, i,
regp->CR58[i]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59,
regp->CRTC[NV_CIO_CRE_59]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_59);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85,
regp->CRTC[NV_CIO_CRE_85]);
- NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86,
regp->CRTC[NV_CIO_CRE_86]);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_85);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_86);
}
NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
@@ -1440,7 +1453,7 @@ static void nv_crtc_save_state_vga(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head,
NV_PRMVIO_MISC__READ);
for (i = 0; i < 25; i++)
- regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
+ crtc_rd_cio_state(crtc, regp, i);
NVSetEnablePalette(pNv, nv_crtc->head, true);
for (i = 0; i < 21; i++)
@@ -1464,23 +1477,23 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
regp = &state->crtc_reg[nv_crtc->head];
- regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_LCD__INDEX);
- regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_RPC0_INDEX);
- regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_RPC1_INDEX);
- regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_LSR_INDEX);
- regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_PIXEL_INDEX);
- regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_HEB__INDEX);
- regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_ENH_INDEX);
-
- regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_FF_INDEX);
- regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_FFLWM__INDEX);
- regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_21);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_LCD__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_RPC1_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_LSR_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HEB__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ENH_INDEX);
+
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_21);
if (pNv->Architecture >= NV_ARCH_30)
- regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_47);
- regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX);
- regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
- regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX);
- regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_ILACE__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_47);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX);
if (pNv->Architecture >= NV_ARCH_10) {
regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
@@ -1497,25 +1510,25 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc,
RIVA_HW_STATE *state)
regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
- regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX);
- regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH4__INDEX);
if (pNv->Architecture >= NV_ARCH_10) {
- regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv,
nv_crtc->head, NV_CIO_CRE_EBR_INDEX);
- regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_CSB);
- regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_4B);
- regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_52);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_EBR_INDEX);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_CSB);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_4B);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_52);
}
/* NV11 and NV20 don't have this, they stop at 0x52. */
if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
for (i = 0; i < 0x10; i++)
regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head,
i);
- regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_59);
- regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_53);
- regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_54);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_59);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_53);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_54);
- regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_85);
- regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head,
NV_CIO_CRE_86);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_85);
+ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_86);
}
regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
commit fe9bfd9b1b5ce6fd0cd0360ec850ae48b4abac41
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Fri Oct 24 21:02:00 2008 +0100
Tidy EnterVT, and don't call it from ScreenInit
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 6e850f7..a169e46 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -623,7 +623,6 @@ NV50AcquireDisplay(ScrnInfoPtr pScrn)
return FALSE;
if (!NV50CursorAcquire(pScrn))
return FALSE;
- xf86SetDesiredModes(pScrn);
return TRUE;
}
@@ -664,38 +663,29 @@ NVEnterVT(int scrnIndex, int flags)
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
NVPtr pNv = NVPTR(pScrn);
- if (!pNv->kms_enable) {
- if (pNv->randr12_enable) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVEnterVT is
called.\n");
- pScrn->vtSema = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVEnterVT is called.\n");
- if (pNv->Architecture == NV_ARCH_50) {
- if (!NV50AcquireDisplay(pScrn))
- return FALSE;
- return TRUE;
- }
-
- /* Save the current state */
- NVSave(pScrn);
+ if (!pNv->kms_enable && pNv->randr12_enable)
+ NVSave(pScrn);
- if (!xf86SetDesiredModes(pScrn))
- return FALSE;
+ if (!pNv->randr12_enable) {
+ if (!NVModeInit(pScrn, pScrn->currentMode))
+ return FALSE;
+ NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
+ } else {
+ pScrn->vtSema = TRUE;
- NVAccelCommonInit(pScrn);
- } else {
- if (!NVModeInit(pScrn, pScrn->currentMode))
+ if (!pNv->kms_enable && pNv->Architecture == NV_ARCH_50)
+ if (!NV50AcquireDisplay(pScrn))
return FALSE;
- NVAdjustFrame(scrnIndex, pScrn->frameX0,
pScrn->frameY0, 0);
- }
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVEnterVT is called.\n");
- if (!xf86SetDesiredModes(pScrn)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"xf86SetDesiredModes failed\n");
+ if (!xf86SetDesiredModes(pScrn))
return FALSE;
- }
}
+ if (!pNv->NoAccel)
+ NVAccelCommonInit(pScrn);
+
if (pNv->overlayAdaptor && pNv->Architecture != NV_ARCH_04)
NV10WriteOverlayParameters(pScrn);
@@ -770,7 +760,6 @@ NVCloseScreen(int scrnIndex, ScreenPtr pScreen)
NVPtr pNv = NVPTR(pScrn);
if (pScrn->vtSema) {
- pScrn->vtSema = FALSE;
#ifdef XF86DRM_MODE
if (pNv->kms_enable) {
NVSync(pScrn);
@@ -1974,17 +1963,7 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc,
char **argv)
}
#endif
- if (!pNv->randr12_enable) {
- /* Save the current state */
- NVSave(pScrn);
- /* Initialise the first mode */
- if (!NVModeInit(pScrn, pScrn->currentMode))
- return FALSE;
-
- /* Darken the screen for aesthetic reasons and set the viewport
*/
- NVSaveScreen(pScreen, SCREEN_SAVER_ON);
- pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0,
0);
- } else {
+ if (pNv->randr12_enable) {
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
@@ -1993,15 +1972,29 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int
argc, char **argv)
xf86_config->crtc[i]->scrn = pScrn;
for (i = 0; i < xf86_config->num_output; i++)
xf86_config->output[i]->scrn = pScrn;
+ }
- pScrn->memPhysBase = pNv->VRAMPhysical;
- pScrn->fbOffset = 0;
+ if (!pNv->kms_enable)
+ NVSave(pScrn);
- if (!NVEnterVT(scrnIndex, 0))
+ if (!pNv->randr12_enable) {
+ if (!NVModeInit(pScrn, pScrn->currentMode))
+ return FALSE;
+ pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0,
0);
+ } else {
+ pScrn->vtSema = TRUE;
+
+ if (!pNv->kms_enable && pNv->Architecture == NV_ARCH_50)
+ if (!NV50AcquireDisplay(pScrn))
+ return FALSE;
+
+ if (!xf86SetDesiredModes(pScrn))
return FALSE;
- NVSaveScreen(pScreen, SCREEN_SAVER_ON);
}
+ /* Darken the screen for aesthetic reasons */
+ if (!pNv->kms_enable)
+ NVSaveScreen(pScreen, SCREEN_SAVER_ON);
/*
* The next step is to setup the screen's visuals, and initialise the
@@ -2208,6 +2201,9 @@ NVSave(ScrnInfoPtr pScrn)
NVPtr pNv = NVPTR(pScrn);
NVRegPtr nvReg = &pNv->SavedReg;
+ if (pNv->Architecture == NV_ARCH_50)
+ return;
+
NVLockVgaCrtcs(pNv, false);
if (pNv->randr12_enable) {
commit 3e1ccff8744d9cabef0cd3901e987deeeb38ec12
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Fri Oct 24 02:49:19 2008 +0100
Condense crtc locking
We unlock all crtcs whenever the driver is active, and relock them when
returning to VT (which is what we were doing, but in a more complicated
manner)
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index eb8de97..10ee1d6 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -70,14 +70,6 @@ static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t
reg, uint32_t val)
NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
}
-void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock)
-{
- struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
- NVPtr pNv = NVPTR(crtc->scrn);
-
- NVLockVgaCrtc(pNv, nv_crtc->head, lock);
-}
-
/* Even though they are not yet used, i'm adding some notes about some of the
0x4000 regs */
/* They are only valid for NV4x, appearantly reordered for NV5x */
/* gpu pll: 0x4000 + 0x4004
@@ -963,9 +955,6 @@ static void nv_crtc_save(xf86CrtcPtr crtc)
if (pNv->twoHeads)
NVSetOwner(pNv, nv_crtc->head);
- /* We just came back from terminal, so unlock */
- NVCrtcLockUnlock(crtc, false);
-
nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
@@ -983,9 +972,6 @@ static void nv_crtc_restore(xf86CrtcPtr crtc)
struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
NVPtr pNv = NVPTR(crtc->scrn);
- /* Just to be safe */
- NVCrtcLockUnlock(crtc, false);
-
if (pNv->twoHeads)
NVSetOwner(pNv, nv_crtc->head);
@@ -1009,9 +995,6 @@ static void nv_crtc_prepare(xf86CrtcPtr crtc)
if (pNv->twoHeads)
NVSetOwner(pNv, nv_crtc->head);
- /* Just in case */
- NVCrtcLockUnlock(crtc, 0);
-
crtc->funcs->dpms(crtc, DPMSModeOff);
/* Sync the engine before adjust mode */
@@ -1324,8 +1307,6 @@ nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
regp->DAC[(i*3)+1] = i;
regp->DAC[(i*3)+2] = i;
}
-
- NVCrtcLockUnlock(crtc, false);
}
static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 2045854..6e850f7 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -667,8 +667,6 @@ NVEnterVT(int scrnIndex, int flags)
if (!pNv->kms_enable) {
if (pNv->randr12_enable) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVEnterVT is
called.\n");
- xf86CrtcConfigPtr xf86_config =
XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
pScrn->vtSema = TRUE;
if (pNv->Architecture == NV_ARCH_50) {
@@ -680,10 +678,6 @@ NVEnterVT(int scrnIndex, int flags)
/* Save the current state */
NVSave(pScrn);
- for (i = 0; i < xf86_config->num_crtc; i++) {
- NVCrtcLockUnlock(xf86_config->crtc[i], 0);
- }
-
if (!xf86SetDesiredModes(pScrn))
return FALSE;
@@ -735,8 +729,6 @@ NVLeaveVT(int scrnIndex, int flags)
}
NVRestore(pScrn);
- if (!pNv->randr12_enable)
- NVLockUnlock(pScrn, 1);
}
static void
@@ -791,8 +783,6 @@ NVCloseScreen(int scrnIndex, ScreenPtr pScreen)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"NVCloseScreen is called.\n");
NVSync(pScrn);
NVRestore(pScrn);
- if (!pNv->randr12_enable)
- NVLockUnlock(pScrn, 1);
}
}
@@ -1384,9 +1374,10 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
nv_crtc_init(pScrn, i);
}
- if (pNv->Architecture < NV_ARCH_50)
+ if (pNv->Architecture < NV_ARCH_50) {
+ NVLockVgaCrtcs(pNv, false);
NvSetupOutputs(pScrn);
- else
+ } else
nv50_output_create(pScrn); /* create randr-1.2
"outputs". */
if (!xf86InitialConfiguration(pScrn, FALSE))
@@ -1712,11 +1703,8 @@ NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
if(!NVDACInit(pScrn, mode))
return FALSE;
- NVLockUnlock(pScrn, 0);
- if(pNv->twoHeads) {
+ if (pNv->twoHeads)
nvWriteCurVGA(pNv, NV_CIO_CRE_44, nvReg->crtcOwner);
- NVLockUnlock(pScrn, 0);
- }
/* Program the registers */
vgaHWProtect(pScrn, TRUE);
@@ -1752,13 +1740,12 @@ NVRestore(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
+ NVLockVgaCrtcs(pNv, false);
+
if (pNv->randr12_enable) {
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
- for (i = 0; i < xf86_config->num_crtc; i++)
- NVCrtcLockUnlock(xf86_config->crtc[i], 0);
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring encoders\n");
for (i = 0; i < pNv->dcb_table.entries; i++)
nv_encoder_restore(pScrn, &pNv->encoders[i]);
@@ -1768,20 +1755,13 @@ NVRestore(ScrnInfoPtr pScrn)
xf86_config->crtc[i]->funcs->restore(xf86_config->crtc[i]);
nv_save_restore_vga_fonts(pScrn, 0);
-
- for (i = 0; i < xf86_config->num_crtc; i++)
- NVCrtcLockUnlock(xf86_config->crtc[i], 1);
} else {
vgaHWPtr hwp = VGAHWPTR(pScrn);
vgaRegPtr vgaReg = &hwp->SavedReg;
NVRegPtr nvReg = &pNv->SavedReg;
- NVLockUnlock(pScrn, 0);
-
- if(pNv->twoHeads) {
+ if (pNv->twoHeads)
nvWriteCurVGA(pNv, NV_CIO_CRE_44, pNv->crtc_active[1] *
0x3);
- NVLockUnlock(pScrn, 0);
- }
/* Only restore text mode fonts/text for the primary card */
vgaHWProtect(pScrn, TRUE);
@@ -1790,11 +1770,11 @@ NVRestore(ScrnInfoPtr pScrn)
}
if (pNv->twoHeads) {
- NVLockVgaCrtc(pNv, 0, false);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring CRTC_OWNER to
%d.\n", pNv->vtOWNER);
NVSetOwner(pNv, pNv->vtOWNER);
- NVLockVgaCrtc(pNv, 0, true);
}
+
+ NVLockVgaCrtcs(pNv, true);
}
static void
@@ -2228,6 +2208,8 @@ NVSave(ScrnInfoPtr pScrn)
NVPtr pNv = NVPTR(pScrn);
NVRegPtr nvReg = &pNv->SavedReg;
+ NVLockVgaCrtcs(pNv, false);
+
if (pNv->randr12_enable) {
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
@@ -2244,11 +2226,8 @@ NVSave(ScrnInfoPtr pScrn)
} else {
vgaHWPtr pVga = VGAHWPTR(pScrn);
vgaRegPtr vgaReg = &pVga->SavedReg;
- NVLockUnlock(pScrn, 0);
- if (pNv->twoHeads) {
+ if (pNv->twoHeads)
nvWriteCurVGA(pNv, NV_CIO_CRE_44, pNv->crtc_active[1] *
0x3);
- NVLockUnlock(pScrn, 0);
- }
NVDACSave(pScrn, vgaReg, nvReg, pNv->Primary);
}
diff --git a/src/nv_hw.c b/src/nv_hw.c
index ad41d95..9960c0f 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -270,7 +270,7 @@ void NVSetOwner(NVPtr pNv, int owner)
}
}
-void NVLockVgaCrtc(NVPtr pNv, int head, bool lock)
+static void NVLockVgaCrtc(NVPtr pNv, int head, bool lock)
{
uint8_t cr11;
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 08732d2..de91c10 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -81,7 +81,6 @@ int get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match,
struct pll_lims *pll
/* nv_crtc.c */
void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y);
void nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num);
-void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock);
/* nv_output.c */
void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder);
@@ -114,7 +113,6 @@ uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index);
void NVVgaSeqReset(NVPtr pNv, int head, bool start);
void NVVgaProtect(NVPtr pNv, int head, bool protect);
void NVSetOwner(NVPtr pNv, int owner);
-void NVLockVgaCrtc(NVPtr pNv, int head, bool lock);
void NVLockVgaCrtcs(NVPtr pNv, bool lock);
void NVBlankScreen(NVPtr pNv, int head, bool blank);
void nv_fix_nv40_hw_cursor(NVPtr pNv, int head);
diff --git a/src/nv_setup.c b/src/nv_setup.c
index a66afb9..b092c32 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -535,7 +535,7 @@ NVCommonSetup(ScrnInfoPtr pScrn)
NVSelectHeadRegisters(pScrn, 0);
- NVLockUnlock(pScrn, 0);
+ NVLockVgaCrtcs(pNv, false);
NVI2CInit(pScrn);
@@ -601,7 +601,6 @@ NVCommonSetup(ScrnInfoPtr pScrn)
nvWriteCurVGA(pNv, NV_CIO_CRE_44, 3);
NVSelectHeadRegisters(pScrn, 1);
- NVLockUnlock(pScrn, 0);
slaved_on_B = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
if(slaved_on_B) {
@@ -610,7 +609,6 @@ NVCommonSetup(ScrnInfoPtr pScrn)
nvWriteCurVGA(pNv, NV_CIO_CRE_44, 0);
NVSelectHeadRegisters(pScrn, 0);
- NVLockUnlock(pScrn, 0);
slaved_on_A = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
if(slaved_on_A) {
diff --git a/src/nv_type.h b/src/nv_type.h
index 41779e6..280b44f 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -523,7 +523,6 @@ typedef struct _NVRec {
#define NVPTR(p) ((NVPtr)((p)->driverPrivate))
#define NVShowHideCursor(pScrn, show) nv_show_cursor(NVPTR(pScrn),
NVPTR(pScrn)->cur_head, show)
-#define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn),
NVPTR(pScrn)->cur_head, lock)
#define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
#define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg,
val)
commit 83b541e0a9c454059d0e55a932a2ecdbbf650d60
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Mon Oct 27 19:20:22 2008 +0000
Common function for the bios condition table
diff --git a/src/nv_bios.c b/src/nv_bios.c
index d010346..042c0d0 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -447,7 +447,31 @@ static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port,
uint8_t data)
}
}
-static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t
offset, uint8_t cond)
+static bool bios_condition_met(ScrnInfoPtr pScrn, bios_t *bios, uint16_t
offset, uint8_t cond)
+{
+ /* The condition table entry has 4 bytes for the address of the
+ * register to check, 4 bytes for a mask to apply to the register and
+ * 4 for a test comparison value
+ */
+
+ uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
+ uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
+ uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
+ uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr +
8])));
+ uint32_t data;
+
+ BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
+ offset, cond, reg, mask);
+
+ data = nv32_rd(pScrn, reg) & mask;
+
+ BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
+ offset, data, cmpval);
+
+ return (data == cmpval);
+}
+
+static bool io_flag_condition_met(ScrnInfoPtr pScrn, bios_t *bios, uint16_t
offset, uint8_t cond)
{
/* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
* for the CRTC index; 1 byte for the mask to apply to the value
@@ -478,10 +502,7 @@ static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset,
BIOSLOG(pScrn, "0x%04X: Checking if 0x%02X equals 0x%02X\n", offset,
data, cmpval);
- if (data == cmpval)
- return true;
-
- return false;
+ return (data == cmpval);
}
int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int
*bestNM, int *bestlog2P)
@@ -1075,7 +1096,7 @@ static bool init_io_restrict_pll(ScrnInfoPtr pScrn,
bios_t *bios, uint16_t offse
freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config *
2])));
if (io_flag_condition_idx > 0) {
- if (io_flag_condition(pScrn, bios, offset,
io_flag_condition_idx)) {
+ if (io_flag_condition_met(pScrn, bios, offset,
io_flag_condition_idx)) {
BIOSLOG(pScrn, "0x%04X: Condition fulfilled --
frequency doubled\n", offset);
freq *= 2;
} else
@@ -1190,7 +1211,7 @@ static bool init_io_flag_condition(ScrnInfoPtr pScrn,
bios_t *bios, uint16_t off
if (!iexec->execute)
return true;
- if (io_flag_condition(pScrn, bios, offset, cond))
+ if (io_flag_condition_met(pScrn, bios, offset, cond))
BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- continuing to
execute\n", offset);
else {
BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- skipping
following commands\n", offset);
@@ -1574,8 +1595,6 @@ static bool init_condition_time(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset
* offset + 2 (8 bit): retries / 50
*
* Check condition "condition number" in the condition table.
- * The condition table entry has 4 bytes for the address of the
- * register to check, 4 bytes for a mask and 4 for a test value.
* Bios code then sleeps for 2ms if the condition is not met, and
* repeats up to "retries" times, but on one C51 this has proved
* insufficient. In mmiotraces the driver sleeps for 20ms, so we do
@@ -1584,37 +1603,26 @@ static bool init_condition_time(ScrnInfoPtr pScrn,
bios_t *bios, uint16_t offset
*/
uint8_t cond = bios->data[offset + 1];
- uint16_t retries = bios->data[offset + 2];
- uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
- uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
- uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
- uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr +
8])));
- uint32_t data = 0;
+ uint16_t retries = bios->data[offset + 2] * 50;
if (!iexec->execute)
return true;
- retries *= 50;
if (retries > 100)
retries = 100;
- BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond,
retries);
-
- for (; retries > 0; retries--) {
- data = nv32_rd(pScrn, reg) & mask;
+ BIOSLOG(pScrn, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", offset,
cond, retries);
- BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
offset, data, cmpval);
-
- if (data != cmpval) {
- BIOSLOG(pScrn, "0x%04X: Condition not met, sleeping for
20ms\n", offset);
- BIOS_USLEEP(20000);
- } else {
+ for (; retries > 0; retries--)
+ if (bios_condition_met(pScrn, bios, offset, cond)) {
BIOSLOG(pScrn, "0x%04X: Condition met, continuing\n",
offset);
break;
+ } else {
+ BIOSLOG(pScrn, "0x%04X: Condition not met, sleeping for
20ms\n", offset);
+ BIOS_USLEEP(20000);
}
- }
- if (data != cmpval) {
+ if (!bios_condition_met(pScrn, bios, offset, cond)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"0x%04X: Condition still not met after %dms, skiping
following opcodes\n",
offset, 20 * retries);
@@ -2232,30 +2240,18 @@ static bool init_condition(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset, ini
* offset + 1 (8 bit): condition number
*
* Check condition "condition number" in the condition table.
- * The condition table entry has 4 bytes for the address of the
- * register to check, 4 bytes for a mask and 4 for a test value.
* If condition not met skip subsequent opcodes until condition is
* inverted (INIT_NOT), or we hit INIT_RESUME
*/
uint8_t cond = bios->data[offset + 1];
- uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
- uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
- uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
- uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr +
8])));
- uint32_t data;
if (!iexec->execute)
return true;
- BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X,
Cmpval: 0x%08X\n",
- offset, cond, reg, mask, cmpval);
-
- data = nv32_rd(pScrn, reg) & mask;
+ BIOSLOG(pScrn, "0x%04X: Condition: 0x%02X\n", offset, cond);
- BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset,
data, cmpval);
-
- if (data == cmpval)
+ if (bios_condition_met(pScrn, bios, offset, cond))
BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- continuing to
execute\n", offset);
else {
BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- skipping
following commands\n", offset);
commit 36c6aa449063387b34c31015d618e53d4b6634e0
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Mon Oct 27 18:55:28 2008 +0000
Allow more time in INIT_CONDITION_TIME (#18234)
diff --git a/src/nv_bios.c b/src/nv_bios.c
index ef358b4..d010346 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -1576,7 +1576,10 @@ static bool init_condition_time(ScrnInfoPtr pScrn,
bios_t *bios, uint16_t offset
* Check condition "condition number" in the condition table.
* The condition table entry has 4 bytes for the address of the
* register to check, 4 bytes for a mask and 4 for a test value.
- * If condition not met sleep for 2ms, and repeat upto "retries" times.
+ * Bios code then sleeps for 2ms if the condition is not met, and
+ * repeats up to "retries" times, but on one C51 this has proved
+ * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
+ * this, and bail after "retries" times, or 2s, whichever is less.
* If still not met after retries, clear execution flag for this table.
*/
@@ -1592,6 +1595,8 @@ static bool init_condition_time(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset
return true;
retries *= 50;
+ if (retries > 100)
+ retries = 100;
BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond,
retries);
@@ -1601,8 +1606,8 @@ static bool init_condition_time(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset
BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
offset, data, cmpval);
if (data != cmpval) {
- BIOSLOG(pScrn, "0x%04X: Condition not met, sleeping for
2ms\n", offset);
- BIOS_USLEEP(2000);
+ BIOSLOG(pScrn, "0x%04X: Condition not met, sleeping for
20ms\n", offset);
+ BIOS_USLEEP(20000);
} else {
BIOSLOG(pScrn, "0x%04X: Condition met, continuing\n",
offset);
break;
@@ -1610,7 +1615,9 @@ static bool init_condition_time(ScrnInfoPtr pScrn, bios_t
*bios, uint16_t offset
}
if (data != cmpval) {
- BIOSLOG(pScrn, "0x%04X: Condition still not met, skiping
following opcodes\n", offset);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "0x%04X: Condition still not met after %dms, skiping
following opcodes\n",
+ offset, 20 * retries);
iexec->execute = false;
}
commit bf810b32bc959f3821bca18cf158f711dd314a26
Author: Stuart Bennett <[EMAIL PROTECTED]>
Date: Mon Oct 27 18:41:43 2008 +0000
More warnings for C51's magical unaligned regs
diff --git a/src/nv_bios.c b/src/nv_bios.c
index 7c97866..ef358b4 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -227,11 +227,16 @@ static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg)
--
To UNSUBSCRIBE, email to [EMAIL PROTECTED]
with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
