debian/changelog | 9
debian/patches/110_fix_intel_965_atunnel_rendering_glitch.diff | 204
++++++++++
debian/patches/series | 1
3 files changed, 214 insertions(+)
New commits:
commit 41730903cb66f975dd2332bc45ee665cf4872c8d
Author: Bryce Harrington <br...@bryceharrington.org>
Date: Thu Mar 12 19:26:05 2009 -0700
Patch from mnemo for atunnel screensaver
diff --git a/debian/changelog b/debian/changelog
index 7971869..bcecb10 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+mesa (7.3-1ubuntu4) jaunty; urgency=low
+
+ * debian/patches/110_fix_intel_965_atunnel_rendering_glitch.diff: fix
rendering defects
+ in atunnel screensaver (from rss-glx package). Patch originally comes from
+ upstream mesa master at cgit.freedesktop.org (26th Feb by Haihao Xiang
+ as commit 68915fd6fac44dd000080298e3afb0669e8754aa). (LP: #330476)
+
+ -- Martin Olsson <mar...@minimum.se> Mon, 02 Mar 2009 13:30:47 +0100
+
mesa (7.3-1ubuntu3) jaunty; urgency=low
* Add 103_rs600_support.patch: Adds support for the RS600 chip and sets
diff --git a/debian/patches/110_fix_intel_965_atunnel_rendering_glitch.diff
b/debian/patches/110_fix_intel_965_atunnel_rendering_glitch.diff
new file mode 100644
index 0000000..7cf590c
--- /dev/null
+++ b/debian/patches/110_fix_intel_965_atunnel_rendering_glitch.diff
@@ -0,0 +1,204 @@
+Index: mesa-7.3/src/mesa/drivers/dri/i965/brw_clip_line.c
+===================================================================
+--- mesa-7.3.orig/src/mesa/drivers/dri/i965/brw_clip_line.c 2009-03-02
13:29:37.000000000 +0100
++++ mesa-7.3/src/mesa/drivers/dri/i965/brw_clip_line.c 2009-03-02
13:30:22.000000000 +0100
+@@ -181,34 +181,54 @@
+ brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1,
c->offset[VERT_RESULT_HPOS]), c->reg.plane_equation);
+ is_negative = brw_IF(p, BRW_EXECUTE_1);
+ {
+- brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0));
+- brw_math_invert(p, c->reg.t, c->reg.t);
+- brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1);
+-
+- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t,
c->reg.t1 );
+- brw_MOV(p, c->reg.t1, c->reg.t);
+- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
++ /*
++ * Both can be negative on GM965/G965 due to RHW workaround
++ * if so, this object should be rejected.
++ */
++ if (!BRW_IS_G4X(p->brw)) {
++ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
c->reg.dp0, brw_imm_f(0.0));
++ is_neg2 = brw_IF(p, BRW_EXECUTE_1);
++ {
++ brw_clip_kill_thread(c);
++ }
++ brw_ENDIF(p, is_neg2);
++ }
++
++ brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0));
++ brw_math_invert(p, c->reg.t, c->reg.t);
++ brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1);
++
++ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t,
c->reg.t1 );
++ brw_MOV(p, c->reg.t1, c->reg.t);
++ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ }
+ is_negative = brw_ELSE(p, is_negative);
+ {
+- /* Coming back in. We know that both cannot be negative
+- * because the line would have been culled in that case.
+- */
+-
+- /* If both are positive, do nothing */
+- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0,
brw_imm_f(0.0));
+- is_neg2 = brw_IF(p, BRW_EXECUTE_1);
++ /* Coming back in. We know that both cannot be negative
++ * because the line would have been culled in that case.
++ */
++
++ /* If both are positive, do nothing */
++ /* Only on GM965/G965 */
++ if (!BRW_IS_G4X(p->brw)) {
++ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L,
c->reg.dp0, brw_imm_f(0.0));
++ is_neg2 = brw_IF(p, BRW_EXECUTE_1);
++ }
++
+ {
+- brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
+- brw_math_invert(p, c->reg.t, c->reg.t);
+- brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
+-
+- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t,
c->reg.t0 );
+- brw_MOV(p, c->reg.t0, c->reg.t);
+- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- }
+- brw_ENDIF(p, is_neg2);
+- }
++ brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
++ brw_math_invert(p, c->reg.t, c->reg.t);
++ brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
++
++ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G,
c->reg.t, c->reg.t0 );
++ brw_MOV(p, c->reg.t0, c->reg.t);
++ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
++ }
++
++ if (!BRW_IS_G4X(p->brw)) {
++ brw_ENDIF(p, is_neg2);
++ }
++ }
+ brw_ENDIF(p, is_negative);
+ }
+ brw_ENDIF(p, plane_active);
+Index: mesa-7.3/src/mesa/drivers/dri/i965/brw_clip_tri.c
+===================================================================
+--- mesa-7.3.orig/src/mesa/drivers/dri/i965/brw_clip_tri.c 2009-03-02
13:29:41.000000000 +0100
++++ mesa-7.3/src/mesa/drivers/dri/i965/brw_clip_tri.c 2009-03-02
13:30:22.000000000 +0100
+@@ -455,6 +455,8 @@
+ struct brw_indirect vt2 = brw_indirect(2, 0);
+
+ struct brw_compile *p = &c->func;
++ struct brw_instruction *is_outside;
++ struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
+
+ brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0]));
+ brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1]));
+@@ -462,53 +464,87 @@
+ brw_MOV(p, v0, deref_4f(vt0, c->offset[VERT_RESULT_HPOS]));
+ brw_MOV(p, v1, deref_4f(vt1, c->offset[VERT_RESULT_HPOS]));
+ brw_MOV(p, v2, deref_4f(vt2, c->offset[VERT_RESULT_HPOS]));
++ brw_AND(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(~0x3f));
+
+ /* test nearz, xmin, ymin plane */
+- brw_CMP(p, t1, BRW_CONDITIONAL_LE, negate(v0), get_element(v0, 3));
++ /* clip.xyz < -clip.w */
++ brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, negate(get_element(v0, 3)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, t2, BRW_CONDITIONAL_LE, negate(v1), get_element(v1, 3));
++ brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, negate(get_element(v1, 3)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, t3, BRW_CONDITIONAL_LE, negate(v2), get_element(v2, 3));
++ brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, negate(get_element(v2, 3)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
++
++ /* All vertices are outside of a plane, rejected */
++ brw_AND(p, t, t1, t2);
++ brw_AND(p, t, t, t3);
++ brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
++ brw_OR(p, tmp0, tmp0, get_element(t, 2));
++ brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
++ brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
++ is_outside = brw_IF(p, BRW_EXECUTE_1);
++ {
++ brw_clip_kill_thread(c);
++ }
++ brw_ENDIF(p, is_outside);
++ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
++
++ /* some vertices are inside a plane, some are outside,need to clip */
+ brw_XOR(p, t, t1, t2);
+ brw_XOR(p, t1, t2, t3);
+ brw_OR(p, t, t, t1);
+-
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 0), brw_imm_ud(0));
++ brw_AND(p, t, t, brw_imm_ud(0x1));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 0), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 1), brw_imm_ud(0));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 1), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 2), brw_imm_ud(0));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 2), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+ /* test farz, xmax, ymax plane */
+- brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, get_element(v0, 3));
++ /* clip.xyz > clip.w */
++ brw_CMP(p, t1, BRW_CONDITIONAL_G, v0, get_element(v0, 3));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, get_element(v1, 3));
++ brw_CMP(p, t2, BRW_CONDITIONAL_G, v1, get_element(v1, 3));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, get_element(v2, 3));
++ brw_CMP(p, t3, BRW_CONDITIONAL_G, v2, get_element(v2, 3));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
++ /* All vertices are outside of a plane, rejected */
++ brw_AND(p, t, t1, t2);
++ brw_AND(p, t, t, t3);
++ brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1));
++ brw_OR(p, tmp0, tmp0, get_element(t, 2));
++ brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
++ brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1));
++ is_outside = brw_IF(p, BRW_EXECUTE_1);
++ {
++ brw_clip_kill_thread(c);
++ }
++ brw_ENDIF(p, is_outside);
++ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
++
++ /* some vertices are inside a plane, some are outside,need to clip */
+ brw_XOR(p, t, t1, t2);
+ brw_XOR(p, t1, t2, t3);
+ brw_OR(p, t, t, t1);
+-
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 0), brw_imm_ud(0));
++ brw_AND(p, t, t, brw_imm_ud(0x1));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 0), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 1), brw_imm_ud(0));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 1), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
+- get_element(t, 2), brw_imm_ud(0));
++ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ,
++ get_element(t, 2), brw_imm_ud(0));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0)));
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
diff --git a/debian/patches/series b/debian/patches/series
index 40f7d3a..74e7488 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -3,4 +3,5 @@
04_osmesa_version.diff
101_ubuntu_hidden_glname.patch
102_dont_vblank.diff
+110_fix_intel_965_atunnel_rendering_glitch.diff
103_rs600_support.patch
--
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