ChangeLog | 24 ++
configure.ac | 2
src/Makefile.am | 5
src/newmmio.h | 6
src/s3.h | 14 +
src/s3_Trio64DAC.c | 72 +++-----
src/s3_accel.c | 16 +
src/s3_driver.c | 347 ++++++++++++++++++++++++++++------------
src/s3_reg.h | 21 ++
src/s3_video.c | 459 +++++++++++++++++++++++++++++------------------------
10 files changed, 609 insertions(+), 357 deletions(-)
New commits:
commit 695868128746b7d8545fd78d1c42ebc2eac00a75
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Dec 22 15:30:39 2008 +1000
s3: fix build by including inputstr.h
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 72c3294..29e7fb5 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -53,6 +53,7 @@
#include "micmap.h"
#include "mibstore.h"
#include "fb.h"
+#include "inputstr.h"
#include "IBM.h"
#include "TI.h"
commit 51e77345fdb5423db233f26d6af4af36887c7059
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Dec 22 15:25:45 2008 +1000
s3 0.6.1
diff --git a/configure.ac b/configure.ac
index 0229c5f..da3284e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-s3],
- 0.6.0,
+ 0.6.1,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-s3)
commit 115436e1ec83e43b1e7727903036720cb109abef
Author: Andrew Randrianasulu <rand...@mail.ru>
Date: Mon Nov 24 12:46:48 2008 -0500
Fix typo in map setup
fixes bug 18688
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 696e8d4..72c3294 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -1131,7 +1131,7 @@ static Bool S3MapMem(ScrnInfoPtr pScrn)
void** result = (void**)&pS3->FBBase;
int err = pci_device_map_range(pS3->PciInfo,
pS3->FBAddress,
- pS3->videoRam * 1024,
+ pScrn->videoRam * 1024,
PCI_DEV_MAP_FLAG_WRITABLE |
PCI_DEV_MAP_FLAG_WRITE_COMBINE,
result);
commit ef1ca4800ee75044243d0eb2346240c50c28f0aa
Author: Adam Jackson <a...@redhat.com>
Date: Fri Aug 15 14:07:28 2008 -0400
Uninclude xf86Version.h
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 86b336c..696e8d4 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -43,7 +43,6 @@
#include "xf86_OSproc.h"
#include "xf86Pci.h"
#include "xf86PciInfo.h"
-#include "xf86Version.h"
#include "xf86Resources.h"
#include "xf86fbman.h"
#include "xf86cmap.h"
commit 565c1ad65277080968c188a635dfd743be7ea2a3
Author: Paulo Cesar Pereira de Andrade <p...@mandriva.com.br>
Date: Thu Jul 17 18:54:17 2008 -0300
Correct unresolved symbol and incorrect assignment.
Function miPointerPosition is deprecated and not available anymore.
Correct "if (test = value)" -> "if (test == value)".
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 797e0b3..86b336c 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -1186,12 +1186,13 @@ static int S3GetPixMuxShift(ScrnInfoPtr pScrn)
shift = 1; /* XXX IBMRGB */
else if (pS3->Chipset == PCI_CHIP_TRIO ||
pS3->Chipset == PCI_CHIP_TRIO64UVP ||
- pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
+ pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) {
if (pS3->s3Bpp == 2)
shift = -1;
else
shift = 0;
-
+ }
+
return shift;
}
@@ -1220,7 +1221,7 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
Set correct blanking for S3 Trio64V2. It's also needed
to clear cr33_5.
*/
- if (pS3->Chipset = PCI_CHIP_TRIO64V2_DXGX)
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
mode->CrtcHBlankStart = mode->CrtcHDisplay + 8;
if ((mode->HTotal == mode->CrtcHTotal) && (pS3->pixMuxShift != 0)) {
@@ -1903,7 +1904,7 @@ static void S3AdjustFrame(int scrnIndex, int x, int y,
int flags)
{
int px, py, a;
- miPointerPosition(&px, &py);
+ miPointerGetPosition(inputInfo.pointer, &px, &py);
if (pS3->s3Bpp == 1)
a = 4 - 1;
commit 2128de2ad9fa67537d8ed56ff173b8a7b0422e0e
Author: Evgeny M. Zubok <evgeny.zu...@tochka.ru>
Date: Mon Jul 7 14:31:10 2008 -0400
S3: various fixes
* src/s3_video.c:
Streams Processor initialization.
XVideo support for 16, 24 and 32 bpp (only for TRIO64V2).
* src/s3_driver.c:
Add XVideo option (enabled by default).
Replace "swcursor" by "hwcursor" option (HW cursor
not implemented yet for all chipsets).
Close bug #5527: 24-bit colour depth support (24bpp and
32bpp framebuffer) for TRIO64V2. Acceleration doesn't work
with packed colour mode (24 bpp FB) but works with 32bpp
framebuffer mode (hardware limitation? -- need data).
Fix system hang-up when switching between console and X session.
Some minor changes of driver messages.
diff --git a/ChangeLog b/ChangeLog
index dc15e51..fab4ec7 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,27 @@
+2008-07-06 Evgeny M. Zubok <evgeny.zu...@tochka.ru>
+
+ * src/s3_video.c:
+
+ Streams Processor initialization.
+
+ XVideo support for 16, 24 and 32 bpp (only for TRIO64V2).
+
+ * src/s3_driver.c:
+
+ Add XVideo option (enabled by default).
+
+ Replace "swcursor" by "hwcursor" option (HW cursor
+ not implemented yet for all chipsets).
+
+ Close bug #5527: 24-bit colour depth support (24bpp and
+ 32bpp framebuffer) for TRIO64V2. Acceleration doesn't work
+ with packed colour mode (24 bpp FB) but works with 32bpp
+ framebuffer mode (hardware limitation? -- need data).
+
+ Fix system hang-up when switching between console and X session.
+
+ Some minor changes of driver messages.
+
2008-02-23 Evgeny M. Zubok <evgeny.zu...@tochka.ru>
* src/s3_driver.c: Add DPMS support for S3 Trio64V2 and possibly
diff --git a/src/Makefile.am b/src/Makefile.am
index 0d9ae4b..743babd 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -39,13 +39,12 @@ s3_drv_la_SOURCES = \
s3_pcirename.h \
s3_reg.h \
s3_Ti.c \
- s3_Trio64DAC.c \
- s3_video.c
+ s3_Trio64DAC.c
noinst_LTLIBRARIES = libs3_accel_newmmio.la libs3_accel_pio.la
s3_drv_la_LIBADD = libs3_accel_newmmio.la libs3_accel_pio.la
-libs3_accel_newmmio_la_SOURCES = s3_accel.c
+libs3_accel_newmmio_la_SOURCES = s3_accel.c s3_video.c
libs3_accel_newmmio_la_CFLAGS = $(AM_CFLAGS) -DS3_NEWMMIO=1
libs3_accel_pio_la_SOURCES = s3_accel.c
diff --git a/src/newmmio.h b/src/newmmio.h
index fdb0d34..e783647 100644
--- a/src/newmmio.h
+++ b/src/newmmio.h
@@ -248,10 +248,10 @@ typedef struct {
#define WaitQueue(v) \
- if(!(pS3->PCIRetry)) { \
+ if(!(pS3->PCIRetry)) { \
mem_barrier(); \
- while(inb(GP_STAT) & (0x0100 >> (v))); \
- }
+ while(INB_GP_STAT() & (0x0100 >> (v))); \
+ }
#define CMD_REG_WIDTH 0x200 /* select 32bit command register */
diff --git a/src/s3.h b/src/s3.h
index 7c59236..a12ff6e 100644
--- a/src/s3.h
+++ b/src/s3.h
@@ -64,7 +64,7 @@ typedef struct _S3RegRec {
typedef struct {
unsigned char brightness;
unsigned char contrast;
- FBAreaPtr area;
+ FBLinearPtr area;
RegionRec clip;
CARD32 colorKey;
CARD32 videoStatus;
@@ -98,12 +98,15 @@ typedef struct _S3Rec {
OptionInfoPtr Options;
unsigned int Flags;
Bool NoAccel;
- Bool SWCursor;
+ Bool HWCursor;
Bool SlowDRAMRefresh;
Bool SlowDRAM;
Bool SlowEDODRAM;
Bool SlowVRAM;
Bool S3NewMMIO;
+ Bool hasStreams;
+ int Streams_FIFO;
+ Bool XVideo;
Bool PCIRetry;
Bool ColorExpandBug;
@@ -159,7 +162,7 @@ typedef struct _S3Rec {
unsigned char *imageBuffer;
int imageWidth;
int imageHeight;
- Bool hwCursor;
+ Bool hwCursor;
} S3Rec, *S3Ptr;
#define S3PTR(p) ((S3Ptr)((p)->driverPrivate))
@@ -234,9 +237,14 @@ Bool S3_CursorInit(ScreenPtr pScreen);
#define S3_964_SERIES() ((pS3->Chipset == PCI_CHIP_964_0) ||
\
(pS3->Chipset == PCI_CHIP_964_1))
+
#define S3_TRIO_SERIES() ((pS3->Chipset == PCI_CHIP_TRIO) ||
\
(pS3->Chipset == PCI_CHIP_AURORA64VP) || \
(pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
(pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
+#define HAS_STREAMS_PROCESSOR() ((pS3->Chipset == PCI_CHIP_AURORA64VP) || \
+ (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
+ (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
+
#endif /* _S3_H */
diff --git a/src/s3_Trio64DAC.c b/src/s3_Trio64DAC.c
index 5b32146..e2cf257 100644
--- a/src/s3_Trio64DAC.c
+++ b/src/s3_Trio64DAC.c
@@ -35,6 +35,7 @@
#include "compiler.h"
#include "s3.h"
+#include "s3_reg.h"
/* this is really quite dumb */
Bool S3Trio64DACProbe(ScrnInfoPtr pScrn)
@@ -232,33 +233,30 @@ static void S3TrioSetPLL(ScrnInfoPtr pScrn, int clk,
unsigned char m,
outb(0x3c4, 0x08);
outb(0x3c5, 0x06); /* unlock extended CR9-18 */
-
- if (clk != 10) {
- outb(0x3c4, 0x12);
- outb(0x3c5, n);
- outb(0x3c4, 0x13);
- outb(0x3c5, m);
-
- outb(0x3c4, 0x15);
- tmp = inb(0x3c5) & ~0x21;
- outb(0x3c5, tmp | 0x02);
- outb(0x3c5, tmp | 0x22);
- outb(0x3c5, tmp | 0x02);
- } else {
- outb(0x3c4, 0x10);
- outb(0x3c5, n);
- outb(0x3c4, 0x11);
- outb(0x3c5, m);
- outb(0x3c4, 0x1a);
- outb(0x3c5, n);
-
- outb(0x3c4, 0x15);
- tmp = inb(0x3c5) & ~0x21;
- outb(0x3c5, tmp | 0x01);
- outb(0x3c5, tmp | 0x21);
- outb(0x3c5, tmp | 0x01);
- outb(0x3c5, tmp);
- }
+
+ outb(0x3c4, 0x12); /* write N1 and N2 to DCLK PLL */
+ outb(0x3c5, n);
+ outb(0x3c4, 0x13); /* write M to DCLK PLL */
+ outb(0x3c5, m);
+
+#if 0
+/* this code was in previous driver version but it was never called.
+ So I decide to comment it. */
+ outb(0x3c4, 0x10);
+ outb(0x3c5, n);
+ outb(0x3c4, 0x11);
+ outb(0x3c5, m); */
+
+ outb(0x3c4, 0x1a);
+ outb(0x3c5, n);
+#endif
+ /* Toggle cr15_5 by sequence 0->1->0 to immediately apply
+ new PLL parameters */
+ outb(0x3c4, 0x15);
+ tmp = inb(0x3c5) & ~0x20;
+ outb(0x3c5, tmp);
+ outb(0x3c5, tmp | 0x20);
+ outb(0x3c5, tmp);
outb(0x3c4, 0x08);
outb(0x3c5, 0x00); /* lock em */
@@ -331,18 +329,17 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr
mode)
S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 31, 0, 3, 2,
135000, 270000);
-
- outb(0x3c4, 1);
+ outb(0x3c4, 0x01);
blank = inb(0x3c5);
outb(0x3c5, blank | 0x20); /* blank the screen */
outb(0x3c4, 0x08);
sr8 = inb(0x3c5);
- outb(0x3c5, 0x06);
+ outb(0x3c5, 0x06); /* unlock extended sequenser register */
- outb(0x3c4, 0x0d0);
- tmp = inb(0x3c5) & ~1;
- outb(0x3c5, tmp);
+ outb(0x3c4, 0x0d);
+ tmp = inb(0x3c5) & ~0x01;
+ outb(0x3c5, tmp); /* VCLK, HSYNC, VSYNC are outputs */
outb(0x3c4, 0x15);
sr15 = inb(0x3c5) & ~0x10;
@@ -352,11 +349,6 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr
mode)
outb(pS3->vgaCRIndex, 0x33);
cr33 = inb(pS3->vgaCRReg) & ~0x28;
- if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
- {
- cr33 |= 0x20;
- }
-
/* ! pixmux */
switch (pScrn->depth) {
case 8:
@@ -369,6 +361,7 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr
mode)
cr33 |= 0x08;
pixmux = 0x50;
break;
+ case 24:
case 32:
pixmux = 0xd0;
break;
@@ -377,6 +370,7 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr
mode)
outb(pS3->vgaCRReg, cr33);
outb(pS3->vgaCRIndex, 0x67);
+ WaitVSync();
outb(pS3->vgaCRReg, pixmux | invert_vclk);
outb(0x3c4, 0x15);
@@ -392,6 +386,6 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr
mode)
outb(0x3c4, 0x08);
outb(0x3c5, sr8);
- outb(0x3c4, 1);
+ outb(0x3c4, 0x01);
outb(0x3c5, blank); /* unblank the screen */
}
diff --git a/src/s3_accel.c b/src/s3_accel.c
index 675b823..78db3b1 100644
--- a/src/s3_accel.c
+++ b/src/s3_accel.c
@@ -140,7 +140,7 @@ static void S3SubsequentScreenToScreenCopy(ScrnInfoPtr
pScrn,
}
}
-
+#if 0
static void S3SetupForColor8x8PatternFill(ScrnInfoPtr pScrn,
int patx, int paty,
int rop, unsigned int planemask,
@@ -182,6 +182,7 @@ static void S3SubsequentColor8x8PatternFillRect(ScrnInfoPtr
pScrn,
SET_MULT_MISC(CMD_REG_WIDTH);
}
}
+#endif
#ifdef S3_NEWMMIO
static void S3SetupForCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
@@ -569,9 +570,22 @@ Bool S3AccelInitPIO(ScreenPtr pScreen)
pXAA->SetupForScreenToScreenCopy = S3SetupForScreenToScreenCopy;
pXAA->SubsequentScreenToScreenCopy = S3SubsequentScreenToScreenCopy;
+ pXAA->ScreenToScreenCopyFlags = NO_TRANSPARENCY;
+#if 0
+/*
+ 8x8 color pattern filling doesn't work properly after introducing
+ framebuffer manager initialization before XAA initialization. There
+ are problems with addressing a colour patterns from offscreen area.
+*/
pXAA->SetupForColor8x8PatternFill = S3SetupForColor8x8PatternFill;
pXAA->SubsequentColor8x8PatternFillRect =
S3SubsequentColor8x8PatternFillRect;
+ pXAA->Color8x8PatternFillFlags = NO_TRANSPARENCY |
+ HARDWARE_PATTERN_SCREEN_ORIGIN |
+ BIT_ORDER_IN_BYTE_MSBFIRST;
+
+ pXAA->CachePixelGranularity = 0;
+#endif
#ifdef S3_NEWMMIO
pXAA->SetupForCPUToScreenColorExpandFill =
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 1a68202..797e0b3 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -152,20 +152,22 @@ static PciChipsets S3PciChipsets[] = {
typedef enum {
OPTION_NOACCEL,
- OPTION_SWCURS,
+ OPTION_HWCURS,
OPTION_SLOW_DRAM_REFRESH,
OPTION_SLOW_DRAM,
OPTION_SLOW_EDODRAM,
- OPTION_SLOW_VRAM
+ OPTION_SLOW_VRAM,
+ OPTION_XVIDEO
} S3Opts;
static OptionInfoRec S3Options[] = {
{ OPTION_NOACCEL, "noaccel", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_SWCURS, "swcursor", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_HWCURS, "hwcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SLOW_DRAM_REFRESH, "slow_dram_refresh", OPTV_BOOLEAN, {0},
FALSE },
{ OPTION_SLOW_DRAM, "slow_dram", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SLOW_EDODRAM, "slow_edodram", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SLOW_VRAM, "slow_vram", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_XVIDEO, "XVideo", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -388,21 +390,20 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
pScrn->monitor = pScrn->confScreen->monitor;
if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support24bppFb | Support32bppFb))
- return FALSE;
+ return FALSE;
switch (pScrn->depth) {
- case 8:
- case 15:
- case 16:
- case 24:
- case 32:
- /* OK */
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Given depth (%d) is not supported by this
driver\n",
- pScrn->depth);
- return FALSE;
+ case 8:
+ case 15:
+ case 16:
+ case 24:
+ /* OK */
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Given depth (%d) is not supported by this
driver\n",
+ pScrn->depth);
+ return FALSE;
}
xf86PrintDepthBpp(pScrn);
@@ -427,37 +428,13 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
xf86CollectOptions(pScrn, NULL);
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, S3Options);
- if (xf86ReturnOptValBool(S3Options, OPTION_NOACCEL, FALSE)) {
- pS3->NoAccel = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: NoAccel -
acceleration disabled\n");
- } else
- pS3->NoAccel = FALSE;
- if (xf86ReturnOptValBool(S3Options, OPTION_SWCURS, FALSE)) {
- pS3->SWCursor = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: SWCursor -
using software cursor\n");
- } else
- pS3->SWCursor = FALSE;
- if (xf86ReturnOptValBool(S3Options, OPTION_SLOW_DRAM_REFRESH, FALSE)) {
- pS3->SlowDRAMRefresh = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: Slow DRAM
Refresh enabled\n");
- } else
- pS3->SlowDRAMRefresh = FALSE;
- if (xf86ReturnOptValBool(S3Options, OPTION_SLOW_DRAM, FALSE)) {
- pS3->SlowDRAM = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: Slow DRAM
enabled\n");
- } else
- pS3->SlowDRAM = FALSE;
- if (xf86ReturnOptValBool(S3Options, OPTION_SLOW_EDODRAM, FALSE)) {
- pS3->SlowEDODRAM = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: Slow EDO DRAM
enabled\n");
- } else
- pS3->SlowEDODRAM = FALSE;
- if (xf86ReturnOptValBool(S3Options, OPTION_SLOW_DRAM, FALSE)) {
- pS3->SlowVRAM = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: Slow VRAM
enabled\n");
- } else
- pS3->SlowVRAM = FALSE;
-
+ pS3->XVideo = xf86ReturnOptValBool(S3Options, OPTION_XVIDEO, TRUE);
+ pS3->NoAccel = xf86ReturnOptValBool(S3Options, OPTION_NOACCEL, FALSE);
+ pS3->HWCursor = xf86ReturnOptValBool(S3Options, OPTION_HWCURS, FALSE);
+ pS3->SlowDRAMRefresh = xf86ReturnOptValBool(S3Options,
OPTION_SLOW_DRAM_REFRESH, FALSE);
+ pS3->SlowDRAM = xf86ReturnOptValBool(S3Options, OPTION_SLOW_DRAM,
FALSE);
+ pS3->SlowEDODRAM = xf86ReturnOptValBool(S3Options, OPTION_SLOW_EDODRAM,
FALSE);
+ pS3->SlowVRAM = xf86ReturnOptValBool(S3Options, OPTION_SLOW_VRAM,
FALSE);
if (pScrn->numEntities > 1) {
S3FreeRec(pScrn);
return FALSE;
@@ -532,6 +509,11 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
break;
}
+ if (HAS_STREAMS_PROCESSOR() && pS3->S3NewMMIO)
+ pS3->hasStreams = TRUE;
+ else
+ pS3->hasStreams = FALSE;
+
pS3->FBAddress = PCI_REGION_BASE(pS3->PciInfo, 0, REGION_MEM);
pScrn->memPhysBase = pS3->FBAddress;
pScrn->fbOffset = 0;
@@ -581,9 +563,10 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
{
+ /* disable DAC power saving to avoid bright left edge */
outb (0x3d4, 0x86);
outb (0x3d5, 0x80);
-
+ /* disable the stream display fetch length control */
outb (0x3d4, 0x90);
outb (0x3d5, 0x00);
}
@@ -664,17 +647,28 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
#endif
switch(pScrn->bitsPerPixel) {
case 8:
- pS3->MaxClock = 135000;
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
+ pS3->MaxClock = 170000;
+ else
+ pS3->MaxClock = 135000;
+
+ pScrn->rgbBits = 6;
break;
case 16:
pS3->MaxClock = 80000;
+ pScrn->rgbBits = 6;
break;
case 24:
case 32:
- pS3->MaxClock = 50000;
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
+ pS3->MaxClock = 56700;
+ else
+ pS3->MaxClock = 50000;
+
+ pScrn->rgbBits = 8;
break;
}
- pScrn->rgbBits = 6;
+
pS3->LoadPalette = S3GenericLoadPalette;
}
@@ -684,7 +678,7 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
return FALSE;
}
- if (pS3->SWCursor)
+ if (!pS3->HWCursor)
pS3->CursorInit = NULL;
pS3->RefClock = S3GetRefClock(pScrn);
@@ -749,6 +743,7 @@ static Bool S3ScreenInit(int scrnIndex, ScreenPtr pScreen,
int argc,
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
S3Ptr pS3 = S3PTR(pScrn);
+ BoxRec ScreenArea;
pScrn->fbOffset = 0;
@@ -811,31 +806,71 @@ static Bool S3ScreenInit(int scrnIndex, ScreenPtr
pScreen, int argc,
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
+ /* framebuffer manager setup */
+ ScreenArea.x1 = 0;
+ ScreenArea.y1 = 0;
+ ScreenArea.x2 = pScrn->displayWidth;
+ ScreenArea.y2 = (pScrn->videoRam * 1024) / pS3->s3BppDisplayWidth;
+
+ if (!xf86InitFBManager(pScreen, &ScreenArea)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Memory manager initialization to (%d,%d) (%d,%d)
failed\n",
+ ScreenArea.x1, ScreenArea.y1,
+ ScreenArea.x2, ScreenArea.y2);
+ return FALSE;
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Memory manager initialized to (%d,%d) (%d,%d)\n",
+ ScreenArea.x1, ScreenArea.y1,
+ ScreenArea.x2, ScreenArea.y2);
+
+
+ /* 2D acceleration setup */
+
+ if (pS3->NoAccel)
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Acceleration disabled (by option)\n");
+
+ /* It seems that acceleration isn't supported for 24-bit packed
+ colour. Disable it for S3 Trio64V2 */
+ if (!pS3->NoAccel && (pScrn->bitsPerPixel == 24) &&
+ (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration isn't
supported for 24 bpp. Disabled.\n");
+ pS3->NoAccel = TRUE;
+ }
+
if (!pS3->NoAccel) {
- if (pS3->S3NewMMIO) {
+ if (pS3->S3NewMMIO)
if (S3AccelInitNewMMIO(pScreen)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Acceleration enabled\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using
NewMMIO\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Acceleration enabled\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using NewMMIO\n");
} else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Acceleration initialization failed\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Acceleration disabled\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Acceleration initialization
failed\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Acceleration disabled\n");
}
- } else {
+ else {
if (S3AccelInitPIO(pScreen)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Acceleration enabled\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using
PIO\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Acceleration enabled\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using PIO\n");
} else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Acceleration initialization failed\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Acceleration disabled\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Acceleration initialization
failed\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Acceleration disabled\n");
}
}
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled by
option\n");
}
-
+
miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
- /* hw cursor setup */
+ /* HW cursor setup */
+
if (pS3->CursorInit) {
if (pS3->CursorInit(pScreen))
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using HW
cursor\n");
@@ -869,10 +904,54 @@ static Bool S3ScreenInit(int scrnIndex, ScreenPtr
pScreen, int argc,
pScrn->racIoFlags = pScrn->racMemFlags = RAC_COLORMAP
| RAC_FB | RAC_VIEWPORT | RAC_CURSOR;
-#if 0
- S3InitVideo(pScreen);
-#endif
+ if (pS3->SlowEDODRAM)
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SlowEDODRAM: Setting 2-cycle EDO\n");
+
+ if (pS3->SlowVRAM)
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SlowVRAM: -RAS low time is 4.5 MCLKs\n");
+
+ if (pS3->SlowDRAM)
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SlowDRAM: -RAS precharge time is 3.5 MCLKs\n");
+
+ if (pS3->SlowDRAMRefresh)
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SlowDRAMRefresh: three refresh cycles per
scanline\n");
+
+ /* XVideo setup */
+
+ if (pS3->XVideo) {
+ if (!pS3->hasStreams) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Overlay video
isn't supported by video hardware. Disabled.\n");
+ pS3->XVideo = FALSE;
+ } else if (pScrn->bitsPerPixel < 16) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Overlay video
isn't supported for %d bpp. Disabled.\n", pScrn->bitsPerPixel);
+ pS3->XVideo = FALSE;
+ }
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Overlay video disabled by option\n");
+ /* At present time we support XV only for chips with New MMIO */
+ if ((pS3->XVideo) && (pS3->S3NewMMIO))
+ S3InitVideo(pScreen);
+
+ switch (pScrn->bitsPerPixel) {
+ case 8:
+ pS3->Streams_FIFO = FIFO_PS16_SS8;
+ break;
+ case 15:
+ case 16:
+ pS3->Streams_FIFO = FIFO_PS12_SS12;
+ break;
+ case 24:
+ case 32:
+ pS3->Streams_FIFO = FIFO_PS8_SS16;
+ break;
+ }
+
return TRUE;
}
@@ -1108,8 +1187,11 @@ static int S3GetPixMuxShift(ScrnInfoPtr pScrn)
else if (pS3->Chipset == PCI_CHIP_TRIO ||
pS3->Chipset == PCI_CHIP_TRIO64UVP ||
pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
- shift = -(pS3->s3Bpp >> 1);
-
+ if (pS3->s3Bpp == 2)
+ shift = -1;
+ else
+ shift = 0;
+
return shift;
}
@@ -1134,13 +1216,22 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn,
DisplayModePtr mode)
pS3->s3ScissB = ((pScrn->videoRam * 1024) / pS3->s3BppDisplayWidth) - 1;
pS3->s3ScissR = pScrn->displayWidth - 1;
- if (mode->HTotal == mode->CrtcHTotal) {
+ /*
+ Set correct blanking for S3 Trio64V2. It's also needed
+ to clear cr33_5.
+ */
+ if (pS3->Chipset = PCI_CHIP_TRIO64V2_DXGX)
+ mode->CrtcHBlankStart = mode->CrtcHDisplay + 8;
+
+ if ((mode->HTotal == mode->CrtcHTotal) && (pS3->pixMuxShift != 0)) {
if (pS3->pixMuxShift > 0) {
/* XXX hack */
/* mode->Flags |= V_PIXMUX; */
mode->CrtcHTotal >>= pS3->pixMuxShift;
mode->CrtcHDisplay >>= pS3->pixMuxShift;
+ mode->CrtcHBlankStart >>= pS3->pixMuxShift;
+ mode->CrtcHBlankEnd >>= pS3->pixMuxShift;
mode->CrtcHSyncStart >>= pS3->pixMuxShift;
mode->CrtcHSyncEnd >>= pS3->pixMuxShift;
mode->CrtcHSkew >>= pS3->pixMuxShift;
@@ -1149,6 +1240,8 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
mode->CrtcHTotal <<= -pS3->pixMuxShift;
mode->CrtcHDisplay <<= -pS3->pixMuxShift;
+ mode->CrtcHBlankStart <<= -pS3->pixMuxShift;
+ mode->CrtcHBlankEnd <<= -pS3->pixMuxShift;
mode->CrtcHSyncStart <<= -pS3->pixMuxShift;
mode->CrtcHSyncEnd <<= -pS3->pixMuxShift;
mode->CrtcHSkew <<= -pS3->pixMuxShift;
@@ -1202,13 +1295,12 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn,
DisplayModePtr mode)
}
/* We need to set this first - S3 *is* broken */
- outw(vgaCRIndex, (pVga->CRTC[17] << 8) | 17);
+ outw(vgaCRIndex, (pVga->CRTC[17] << 8) | 17);
for(r=0; r<25; r++)
outw(vgaCRIndex, (pVga->CRTC[r] << 8) | r);
- for(r=0; r<9; r++) {
+ for(r=0; r<9; r++)
outw(0x3ce, (pVga->Graphics[r] << 8) | r);
- }
inb(vgaIOBase + 0x0a);
@@ -1235,19 +1327,14 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn,
DisplayModePtr mode)
if ((pS3->Chipset == PCI_CHIP_964_0) ||
(pS3->Chipset == PCI_CHIP_964_1))
new->cr33 = 0x20;
+ else if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
+ new->cr33 &= ~0x20;
outb(vgaCRReg, new->cr33);
new->cr34 = 0x10;
outb(vgaCRIndex, 0x34);
outb(vgaCRReg, new->cr34);
- if (pS3->SlowDRAMRefresh)
- new->cr3a = 0xb7;
- else
- new->cr3a = 0xb5;
- outb(vgaCRIndex, 0x3a);
- outb(vgaCRReg, new->cr3a);
-
if (pS3->Chipset != PCI_CHIP_AURORA64VP) {
new->cr3b = (pVga->CRTC[0] + pVga->CRTC[4] + 1) / 2;
outb(vgaCRIndex, 0x3b);
@@ -1302,7 +1389,7 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
tmp |= 0x10;
break;
case 24:
- tmp |= 0x20;
+ tmp |= 0x20; /* there is no such value in spec s3.txt */
break;
case 32:
tmp |= 0x30;
@@ -1373,6 +1460,16 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
new->cr60 = n;
outb(vgaCRReg, new->cr60);
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) {
+ new->cr60 = 255;
+ outb(vgaCRIndex, 0x60);
+ outb(vgaCRReg, new->cr60);
+
+ new->cr54 = 31 << 3;
+ outb(vgaCRIndex, 0x54);
+ outb(vgaCRReg, new->cr54);
+ }
+
outb(vgaCRIndex, 0x55);
new->cr55 = (inb(vgaCRReg) & 0x08) | 0x40;
outb(vgaCRReg, new->cr55);
@@ -1387,10 +1484,10 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn,
DisplayModePtr mode)
{
int i;
unsigned int j;
-
- i = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8) |
- ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7) |
- ((((mode->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6) |
+
+ i = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8) |
+ ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7) |
+ ((((mode->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6) |
((mode->CrtcHSyncStart & 0x800) >> 7);
if ((mode->CrtcHSyncEnd >> 3) - (mode->CrtcHSyncStart >> 3) >
64)
i |= 0x08;
@@ -1452,6 +1549,33 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
outb(vgaCRReg, new->cr42);
}
+ if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) {
+ unsigned char a;
+
+ outb(vgaCRIndex, 0x67);
+ a = inb(vgaCRReg) & 0xfe;
+
+ switch (pScrn->depth) {
+ case 8:
+ break;
+ case 15:
+ a |= (3 << 4);
+ break;
+ case 16:
+ a |= (5 << 4);
+ break;
+ case 24:
+ a |= (13 << 4);
+ break;
+ }
+
+ if (pS3->hasStreams)
+ a |= (3 << 2);
+
+ WaitVSync(); /* Wait for VSync before setting mode */
+ outb(vgaCRReg, a);
+ }
+
if (pS3->Chipset == PCI_CHIP_968) {
unsigned char a;
@@ -1513,6 +1637,35 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
new->cr66 |= 0x80;
outb(vgaCRReg, new->cr66);
+ if (pS3->SlowDRAMRefresh)
+ new->cr3a = 0xb7;
+ else
+ new->cr3a = 0xb5;
+ outb(vgaCRIndex, 0x3a);
+ outb(vgaCRReg, new->cr3a);
+
+ /*
+ Set 3.5 MCLKs for -RAS low, 2.5 MCLKs for -RAS precharge,
+ disable -CAS/-OE adjustment. It seems that cr68 has different
+ format for 96x and TRIOs
+ */
+ if (!((pS3->Chipset == PCI_CHIP_968) ||
+ (pS3->Chipset == PCI_CHIP_964_0) ||
+ (pS3->Chipset == PCI_CHIP_964_1))) {
+
+ outb(vgaCRIndex, 0x39);
+ outb(vgaCRReg, 0xa5);
+
+ outb(vgaCRIndex, 0x68);
+ tmp = inb(vgaCRReg) & ~0x0f;
+ outb(vgaCRReg, tmp | 0x0f);
+
+ /* Enable 1-cycle EDO access */
+ outb(vgaCRIndex, 0x36);
+ tmp = inb(vgaCRReg);
+ outb(vgaCRReg, tmp & 0xf3);
+ }
+
if (pS3->SlowVRAM) {
/*
* some Diamond Stealth 64 VRAM cards have a problem with
@@ -1530,7 +1683,7 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
if (pS3->SlowDRAM) {
/*
* fixes some pixel errors for a SPEA Trio64V+ card
- * increas -RAS precharge timing from 2.5 MCLKs
+ * increase -RAS precharge timing from 2.5 MCLKs
* to 3.5 MCLKs
*/
outb(vgaCRIndex, 0x39);
@@ -1543,7 +1696,7 @@ static Bool S3ModeInit(ScrnInfoPtr pScrn, DisplayModePtr
mode)
if (pS3->SlowEDODRAM) {
--
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