The branch stable/13 has been updated by markj: URL: https://cgit.FreeBSD.org/src/commit/?id=7e27397935dc467e871e36a266dea06e112f8dfc
commit 7e27397935dc467e871e36a266dea06e112f8dfc Author: Mark Johnston <[email protected]> AuthorDate: 2022-03-01 14:06:03 +0000 Commit: Mark Johnston <[email protected]> CommitDate: 2022-03-14 14:45:38 +0000 riscv: Try to improve the comments for locore's page table setup No functional change intended. Reviewed by: jhb Sponsored by: The FreeBSD Foundation (cherry picked from commit 43379792365130b1fa338c310f00aa6821493ead) --- sys/riscv/riscv/locore.S | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S index 28e68c1d6057..bf0ac8e122be 100644 --- a/sys/riscv/riscv/locore.S +++ b/sys/riscv/riscv/locore.S @@ -107,7 +107,16 @@ _start: mv a1, zero /* - * Page tables setup + * Set up page tables: map a 1GB region starting at KERNBASE using 2MB + * superpages, starting from the first 2MB physical page into which the + * kernel was loaded. Also reserve an L2 page for the early device map + * and map the DTB, if any, using the second-last entry of that L2 + * page. This is hopefully enough to get us to pmap_bootstrap(). + * + * Implementations are required to provide SV39 mode, so we use that + * initially and will optionally enable SV48 mode during kernel pmap + * initialization. + * * a0 - modulep or zero * a1 - zero or dtbp */ @@ -122,7 +131,7 @@ pagetables: li a5, KERNBASE srli a5, a5, L1_SHIFT /* >> L1_SHIFT */ - andi a5, a5, 0x1ff /* & 0x1ff */ + andi a5, a5, Ln_ADDR_MASK /* & Ln_ADDR_MASK */ li t4, PTE_V slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */ or t6, t4, t5 @@ -148,19 +157,19 @@ pagetables: addi t4, t4, 1 bltu t4, t3, 1b - /* Create an L1 page for early devmap */ + /* Create an L1 table entry for early devmap */ lla s1, pagetable_l1 lla s2, pagetable_l2_devmap /* Link to next level PN */ srli s2, s2, PAGE_SHIFT li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE) srli a5, a5, L1_SHIFT /* >> L1_SHIFT */ - andi a5, a5, 0x1ff /* & 0x1ff */ + andi a5, a5, Ln_ADDR_MASK /* & Ln_ADDR_MASK */ li t4, PTE_V slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */ or t6, t4, t5 - /* Store single level1 PTE entry to position */ + /* Store the L1 table entry */ li a6, PTE_SIZE mulw a5, a5, a6 add t0, s1, a5 @@ -169,7 +178,7 @@ pagetables: /* Check if we have a DTB that needs to be mapped */ beqz a1, 2f - /* Create an L2 page superpage for DTB */ + /* Create an L2 mapping for the DTB */ lla s1, pagetable_l2_devmap mv s2, a1 srli s2, s2, PAGE_SHIFT @@ -180,7 +189,7 @@ pagetables: slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */ or t0, t0, t2 - /* Store PTE entry to position */ + /* Store the L2 table entry for the DTB */ li a6, PTE_SIZE li a5, 510 mulw a5, a5, a6
