The branch main has been updated by jhb:
URL:
https://cgit.FreeBSD.org/src/commit/?id=613e07c07f3b069eae08d9c5f5642713621c4a43
commit 613e07c07f3b069eae08d9c5f5642713621c4a43
Author: John Baldwin <j...@freebsd.org>
AuthorDate: 2022-04-13 00:11:28 +0000
Commit: John Baldwin <j...@freebsd.org>
CommitDate: 2022-04-13 00:11:28 +0000
smc: Rename constants for control register from CTR* to CTRL*.
This avoids a conflict with the recently-added CTR macro in
<sys/ktr.h>.
---
sys/dev/smc/if_smc.c | 6 +++---
sys/dev/smc/if_smcreg.h | 18 +++++++++---------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/sys/dev/smc/if_smc.c b/sys/dev/smc/if_smc.c
index c8cd345596ce..830a8af82923 100644
--- a/sys/dev/smc/if_smc.c
+++ b/sys/dev/smc/if_smc.c
@@ -1175,9 +1175,9 @@ smc_reset(struct smc_softc *sc)
* Set up the control register.
*/
smc_select_bank(sc, 1);
- ctr = smc_read_2(sc, CTR);
- ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
- smc_write_2(sc, CTR, ctr);
+ ctr = smc_read_2(sc, CTRL);
+ ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE;
+ smc_write_2(sc, CTRL, ctr);
/*
* Reset the MMU.
diff --git a/sys/dev/smc/if_smcreg.h b/sys/dev/smc/if_smcreg.h
index 4642966f0d49..2705cff1dee5 100644
--- a/sys/dev/smc/if_smcreg.h
+++ b/sys/dev/smc/if_smcreg.h
@@ -140,15 +140,15 @@
#define GPR 0xa
/* Bank 1, Offset 0xc: Control Register */
-#define CTR 0xa
-#define CTR_STORE 0x0001 /* Store registers to EEPROM */
-#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM
*/
-#define CTR_EEPROM_SELECT 0x0004 /* Select registers to
store/reload */
-#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH
interrupt */
-#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH
interrupt */
-#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH
interrupt */
-#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX
packets */
-#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC
packets */
+#define CTRL 0xa
+#define CTRL_STORE 0x0001 /* Store registers to EEPROM */
+#define CTRL_RELOAD 0x0002 /* Reload registers from EEPROM
*/
+#define CTRL_EEPROM_SELECT 0x0004 /* Select registers to
store/reload */
+#define CTRL_TE_ENABLE 0x0020 /* TX error causes EPH
interrupt */
+#define CTRL_CR_ENABLE 0x0040 /* Ctr rollover causes EPH
interrupt */
+#define CTRL_LE_ENABLE 0x0080 /* Link error causes EPH
interrupt */
+#define CTRL_AUTO_RELEASE 0x0800 /* Automatically release TX
packets */
+#define CTRL_RCV_BAD 0x4000 /* Receive/discard bad CRC
packets */
/* Bank 2, Offset 0x0: MMU Command Register */
#define MMUCR 0x0
