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new 4ac1d326 Fix RISC-V cpu_relax: use pause hint instead of fence.i
(#3374)
4ac1d326 is described below
commit 4ac1d32605061f851853f2bfec40c1341f0ff7cc
Author: Felix-Gong <[email protected]>
AuthorDate: Thu Jul 9 20:51:46 2026 +0800
Fix RISC-V cpu_relax: use pause hint instead of fence.i (#3374)
fence.i is an instruction-synchronization barrier that flushes the icache,
too heavy for a spin-wait hint. Use the pause hint (Zihintpause extension,
encoding 0x0100000F) instead, matching the RISC-V Linux kernel's
ALT_RISCV_PAUSE() behavior.
.word is used to emit the raw encoding for maximum assembler compatibility,
avoiding dependency on either the 'pause' mnemonic (requires Zihintpause in
-march) or the .insn directive (requires recent binutils/Clang).
Signed-off-by: Xiaofei Gong <[email protected]>
Signed-off-by: YuanSheng <[email protected]>
---
src/bthread/processor.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/bthread/processor.h b/src/bthread/processor.h
index 246c8b93..06e75641 100644
--- a/src/bthread/processor.h
+++ b/src/bthread/processor.h
@@ -29,7 +29,14 @@
#if defined(ARCH_CPU_ARM_FAMILY)
# define cpu_relax() asm volatile("yield\n": : :"memory")
#elif defined(ARCH_CPU_RISCV_FAMILY)
-# define cpu_relax() asm volatile("fence.i\n": : :"memory")
+// Use the pause hint (Zihintpause extension). Encoding 0x0100000F
+// (fence 0, 1) is a HINT on all RISC-V implementations: it never traps
+// and is ignored on CPUs without Zihintpause. On CPUs with Zihintpause
+// it provides a multi-cycle stall hint that reduces power and improves
+// resource fairness during spin-wait loops. Matches the Linux kernel's
+// RISC-V cpu_relax() behavior. .word is used instead of .insn or the
+// pause mnemonic for maximum assembler compatibility.
+# define cpu_relax() asm volatile(".word 0x0100000f\n": : :"memory")
#elif defined(ARCH_CPU_LOONGARCH64_FAMILY)
# define cpu_relax() asm volatile("nop\n": : :"memory");
#else
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