tisonkun commented on code in PR #196:
URL: https://github.com/apache/datasketches-rust/pull/196#discussion_r3754825616


##########
datasketches/src/hll/mod.rs:
##########
@@ -42,24 +42,29 @@
 //!
 //! # HLL Types
 //!
-//! Three target HLL types are supported, trading precision for memory:
+//! The three target HLL types are isomorphic representations of the same 
registers. Given the
+//! same `lg_k` and input, they produce identical estimates and error 
distributions; they trade
+//! memory layout and update performance, not statistical precision:
 //!
-//! * [`HllType::Hll4`]: 4 bits per bucket (most compact)
-//! * [`HllType::Hll6`]: 6 bits per bucket (balanced)
-//! * [`HllType::Hll8`]: 8 bits per bucket (highest precision)
+//! * [`HllType::Hll4`]: 4 bits per bucket plus an auxiliary table for rare 
exceptions (most
+//!   compact)
+//! * [`HllType::Hll6`]: 6 bits per bucket (fixed-size middle ground)

Review Comment:
   ```suggestion
   //! * [`HllType::Hll4`]: 4 bits per bucket (most compact)
   ```
   
   Need not expose internal concepts.



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