The mempool is setup to not cache the packets and the order you send the packets will be the same order they appear on the wire. Also packets are stored on the TX done queue and it is hard to get the queue to flush them back to the mempool. Even after you stop sending packets you can still have packets on the TX ring in the done state, but not flushed to the mempool list. The only way I have found to clean the TX done queue is to disable the port and reenable it again. :-(
In Pktgen the packets are read into memory and then copied into the mempool of tx packet and place back on the mempool free list. In one of the previous versions of Pktgen if the TX ring becomes full then the packets were being freed back to the mempool. The mempool should put the freed packet on the end of the free list to maintain order, but because the TX done ring is not cleaned up the freed packets are getting placed on the mempool list out of order. Not sure what is really happening to you as I do not have enough information to determine the problem. Please make sure you have the latest Pktgen version. Keith Wiles, Principal Technologist for Networking member of the CTO office, Wind River mobile 972.213.5533 [Powering 30 Years of Innovation]<http://www.windriver.com/announces/wr30/> On Feb 4, 2014, at 8:51 PM, Banashankar KV <banveerad at gmail.com<mailto:banveerad at gmail.com>> wrote: Hi, I am trying to send out modified pcap packets in a loop as shown below.I am trying to modify source IP and source port. for each *packet[12 in number]* for each *sip[2 in number]* for each *port[10 in number]* change to *port *and *sip *in *packet* ret = rte_eth_tx_burst(.....) For the 6th packet, 80% of the packets sent out are same wrong packet and other time i see the same other packet 2-3 times instead of the correct packet. But if I place a breakpoint and send the packets one after the other, all the packets have their respective modified port and source IP. I am not able to figure out why it's behaving like this. is there any caching of the packets or something like that? In rte_mempool_create I see its passing 0 for cache size. Thanks Banashankar
