On Wed, Mar 19, 2014 at 09:22:03PM -0700, H. Peter Anvin wrote:
> On 03/19/2014 05:40 PM, Neil Horman wrote:
> > So after some discussion with hpa, I need to self NAK this again, apologies
> > for
> > the noise. Theres some clean up to be done in this area, and I'm still
> > getting
> > a segfault that is in some way related to this code, but I need to dig
> > deeper to
> > understand it.
> >
> > Neil
>
> I still believe we should add the patch I posted in the previous email;
> I should clean it up and put a proper header on it.
>
I agree, but the fact of the matter is that I'm still getting a segfault very
close to these instructions and I dont' understand why yet. I'd hate to just
make the problem go away without understanding the reason why. The patch you
propose doesn't fix (yet moving the xchgl to its own asm statement does).
> This is, if there is actually a need to feed %ebx and %edx into CPUID
> (the native instruction is sensitive to %eax and %ecx, but not %ebx or
> %edx.)
>
> For reference, this is a version of CPUID I personally often use:
>
> struct cpuid {
> unsigned int eax, ecx, edx, ebx;
> };
>
> static inline void cpuid(unsigned int leaf, unsigned int subleaf,
> struct cpuid *out)
> {
> #if defined(__i386__) && defined(__PIC__)
So, this is an additional difference and this in fact does make the problem
clear up. By applying only this patch:
@@ -192,7 +192,7 @@ rte_cpu_get_features(struct cpuid_parameters_t params)
{
int eax, ebx, ecx, edx; /* registers */
-#ifndef __PIC__
+#if !defined(__PIC__) || !defined(__i386__)
asm volatile ("cpuid"
/* output */
: "=a" (eax),
my build compiles the cpuid instruction branch, not the mov;cpuid; xchgl branch
(its an x86_64 build). Is there any reason that x86_64 doesn't need to save the
ebx register when running cpuid while building PIE code?
Neil
