> -----Original Message-----
> From: dev <dev-boun...@dpdk.org> On Behalf Of Gage Eads
> Sent: Wednesday, January 16, 2019 6:33 AM
> To: dev@dpdk.org
> Cc: olivier.m...@6wind.com; arybche...@solarflare.com;
> bruce.richard...@intel.com; konstantin.anan...@intel.com
> Subject: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only)
>
> This operation can be used for non-blocking algorithms, such as a
> non-blocking stack or ring.
>
> Signed-off-by: Gage Eads <gage.e...@intel.com>
> ---
>  .../common/include/arch/x86/rte_atomic_64.h        | 22
> ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> index fd2ec9c53..34c2addf8 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h
> @@ -34,6 +34,7 @@
>  /*
>   * Inspired from FreeBSD src/sys/amd64/include/atomic.h
>   * Copyright (c) 1998 Doug Rabson
> + * Copyright (c) 2019 Intel Corporation
>   * All rights reserved.
>   */
>
> @@ -208,4 +209,25 @@ static inline void
> rte_atomic64_clear(rte_atomic64_t *v)
>  }
>  #endif
>
> +static inline int
> +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t
> *src)
> +{
> +uint8_t res;
> +
> +asm volatile (
> +      MPLOCKED
> +      "cmpxchg16b %[dst];"
> +      " sete %[res]"
> +      : [dst] "=m" (*dst),
> +[res] "=r" (res)
> +      : "c" (src[1]),
> +"b" (src[0]),
> +"m" (*dst),
> +"d" (exp[1]),
> +"a" (exp[0])
> +      : "memory");
> +
> +return res;
> +}
> +

CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK=y can't coexist with RTE_FORCE_INTRINSICS=y, 
this should be explicitly described somewhere in the configuration and 
documentations.

>  #endif /* _RTE_ATOMIC_X86_64_H_ */
> --
> 2.13.6

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