>
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <d...@linux.vnet.ibm.com>
> ---
> v2:
> * Removed ifdef's for PPC since the rte_smp_*mb() macros are already
> customized for each CPU architecture
>
> app/test/test_barrier.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
> index a022708..0bf82cf 100644
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -92,12 +92,14 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> + rte_smp_wmb();
> l->victim = self;
>
> store_load_barrier(l->utype);
>
> while (l->flag[other] == 1 && l->victim == self)
> rte_pause();
> + rte_smp_rmb();
> }
>
> static void
> --
Acked-by: Konstantin Ananyev <konstantin.anan...@intel.com>
> 1.8.3.1
