> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jer...@marvell.com>
> Sent: Monday, July 22, 2019 6:20 PM
> To: Phil Yang (Arm Technology China) <phil.y...@arm.com>; dev@dpdk.org
> Cc: tho...@monjalon.net; gage.e...@intel.com;
> hemant.agra...@nxp.com; Honnappa Nagarahalli
> <honnappa.nagaraha...@arm.com>; Gavin Hu (Arm Technology China)
> <gavin...@arm.com>; nd <n...@arm.com>
> Subject: RE: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare
> exchange
>
> > -----Original Message-----
> > From: Phil Yang <phil.y...@arm.com>
> > Sent: Monday, July 22, 2019 2:14 PM
> > To: dev@dpdk.org
> > Cc: tho...@monjalon.net; Jerin Jacob Kollanukkaran
> <jer...@marvell.com>;
> > gage.e...@intel.com; hemant.agra...@nxp.com;
> > honnappa.nagaraha...@arm.com; gavin...@arm.com; n...@arm.com
> > Subject: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare
> exchange
> > Add 128-bit atomic compare exchange on aarch64.
> >
> > Suggested-by: Jerin Jacob <jer...@marvell.com>
> > Signed-off-by: Phil Yang <phil.y...@arm.com>
> > Tested-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> > +
> > +#
> > +# Compile ARM LSE ATOMIC instructions statically #
>
> There is NO value for the keyword "statically" here. Right?
Agree. Will remove it.
>
> > +CONFIG_RTE_ARM_FEATURE_ATOMICS=n
>
>
> > diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > index cc5c64b..17b6dec 100644
> > --- a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > @@ -6,6 +6,7 @@
> >
> > CONFIG_RTE_MACHINE="thunderx2"
> >
> > +CONFIG_RTE_ARM_FEATURE_ATOMICS=y
>
>
> Add for octeontx2 as well.
OK. Will add it in v5.
>
> > CONFIG_RTE_CACHE_LINE_SIZE=64
> > CONFIG_RTE_MAX_NUMA_NODES=2
> > CONFIG_RTE_MAX_LCORE=256
>
>
> > +rte_atomic128_cmp_exchange(rte_int128_t *dst,
> > + rte_int128_t *exp,
> > + const rte_int128_t *src,
> > + unsigned int weak,
> > + int success,
> > + int failure)
> > +{
> > + /* Always do strong CAS */
> > + RTE_SET_USED(weak);
> > + /* Ignore memory ordering for failure, memory order for
> > + * success must be stronger or equal
> > + */
> > + RTE_SET_USED(failure);
> > + /* Find invalid memory order */
> > + RTE_ASSERT(success == __ATOMIC_RELAXED
> > + || success == __ATOMIC_ACQUIRE
> > + || success == __ATOMIC_RELEASE
> > + || success == __ATOMIC_ACQ_REL
> > + || success == __ATOMIC_SEQ_CST);
> > +
> > +#ifdef __ARM_FEATURE_ATOMICS
>
> Shouldn't it be #if defined(__ARM_FEATURE_ATOMICS) ||
> defined(RTE_ARM_FEATURE_ATOMICS) ?
Yes. That was a mistake. Will update in the version 5. Thanks.
Thanks,
Phil Yang
