On 09/26, alvinx.zh...@intel.com wrote:
>From: Alvin Zhang <alvinx.zh...@intel.com>
>
>If support-multi-driver is enabled, the global registers should not
>be configured. But with the correct code base, if creating a flow

correct -> current

>with rte_flow API, the global register GLQF_FD_MSK may be changed.
>
>Fixes: cfdfca493cae ("net/i40e: fix multiple driver support")
>Cc: sta...@dpdk.org
>
>Signed-off-by: Alvin Zhang <alvinx.zh...@intel.com>
>--
>
>v2: modify codes according to the comments.
>---
> drivers/net/i40e/i40e_flow.c | 34 +++++++++++++++++++++++++++-------
> 1 file changed, 27 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
>index e902a35..9dd7b13 100644
>--- a/drivers/net/i40e/i40e_flow.c
>+++ b/drivers/net/i40e/i40e_flow.c
>@@ -2349,6 +2349,33 @@ static int i40e_flow_destroy_tunnel_filter(struct 
>i40e_pf *pf,
>       if (num < 0)
>               return -EINVAL;
> 
>+      if (pf->support_multi_driver) {
>+              for (i = 0; i < num; i++)
>+                      if (i40e_read_rx_ctl(hw,
>+                                      I40E_GLQF_FD_MSK(i, pctype)) !=
>+                                      mask_reg[i]) {
>+                              PMD_DRV_LOG(ERR, "Input set setting is not"
>+                                              " supported.");

Could you mention multi-driver in the err log? otherwise this info is 
misleading.

>+                              return -EPERM;
>+                      }
>+              for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
>+                      if (i40e_read_rx_ctl(hw,
>+                                      I40E_GLQF_FD_MSK(i, pctype)) != 0) {
>+                              PMD_DRV_LOG(ERR, "Input set setting is not"
>+                                              " supported.");

Ditto.

Thanks,
Xiaolong

>+                              return -EPERM;
>+                      }
>+
>+      } else {
>+              for (i = 0; i < num; i++)
>+                      i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
>+                              mask_reg[i]);
>+              /*clear unused mask registers of the pctype */
>+              for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
>+                      i40e_check_write_reg(hw,
>+                                      I40E_GLQF_FD_MSK(i, pctype), 0);
>+      }
>+
>       inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
> 
>       i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
>@@ -2357,13 +2384,6 @@ static int i40e_flow_destroy_tunnel_filter(struct 
>i40e_pf *pf,
>                            (uint32_t)((inset_reg >>
>                                        I40E_32_BIT_WIDTH) & UINT32_MAX));
> 
>-      for (i = 0; i < num; i++)
>-              i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
>-                                   mask_reg[i]);
>-
>-      /*clear unused mask registers of the pctype */
>-      for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
>-              i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
>       I40E_WRITE_FLUSH(hw);
> 
>       pf->fdir.input_set[pctype] = input_set;
>-- 
>1.8.3.1
>

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