From: Kalesh AP <kalesh-anakkur.pura...@broadcom.com>
HWRM_ERROR_RECOVERY_QCFG command returns the FW status registers offset
for periodic firmware health check monitoring. Map them to GRC window 2.
Signed-off-by: Kalesh AP <kalesh-anakkur.pura...@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.ko...@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khapa...@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 22 +++++++++++++++++++++-
drivers/net/bnxt/bnxt_ethdev.c | 34 ++++++++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_hwrm.c | 4 ++++
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index bfe5cb0df2..ac2bf158dd 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -354,7 +354,9 @@ struct bnxt_error_recovery_info {
#define BNXT_FW_HEARTBEAT_CNT_REG 1
#define BNXT_FW_RECOVERY_CNT_REG 2
#define BNXT_FW_RESET_INPROG_REG 3
- uint32_t status_regs[4];
+#define BNXT_FW_STATUS_REG_CNT 4
+ uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
+ uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
uint32_t reset_inprogress_reg_mask;
#define BNXT_NUM_RESET_REG 16
uint8_t reg_array_cnt;
@@ -366,6 +368,22 @@ struct bnxt_error_recovery_info {
uint32_t flags;
};
+/* address space location of register */
+#define BNXT_FW_STATUS_REG_TYPE_MASK 3
+/* register is located in PCIe config space */
+#define BNXT_FW_STATUS_REG_TYPE_CFG 0
+/* register is located in GRC address space */
+#define BNXT_FW_STATUS_REG_TYPE_GRC 1
+/* register is located in BAR0 */
+#define BNXT_FW_STATUS_REG_TYPE_BAR0 2
+/* register is located in BAR1 */
+#define BNXT_FW_STATUS_REG_TYPE_BAR1 3
+
+#define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
+#define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
+
+#define BNXT_GRCP_WINDOW_2_BASE 0x2000
+
#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
struct bnxt {
void *bar0;
@@ -511,6 +529,8 @@ int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int
wait_to_complete);
int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
int is_bnxt_in_error(struct bnxt *bp);
+int bnxt_map_fw_health_status_regs(struct bnxt *bp);
+
bool is_bnxt_supported(struct rte_eth_dev *dev);
bool bnxt_stratus_device(struct bnxt *bp);
extern const struct rte_flow_ops bnxt_flow_ops;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 95d63435bb..a23ca2b53d 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -3562,6 +3562,40 @@ static const struct eth_dev_ops bnxt_dev_ops = {
.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
};
+int bnxt_map_fw_health_status_regs(struct bnxt *bp)
+{
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t reg_base = 0xffffffff;
+ int i;
+
+ /* Only pre-map the monitoring GRC registers using window 2 */
+ for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
+ uint32_t reg = info->status_regs[i];
+
+ if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
+ continue;
+
+ if (reg_base == 0xffffffff)
+ reg_base = reg & 0xfffff000;
+ if ((reg & 0xfffff000) != reg_base)
+ return -ERANGE;
+
+ /* Use mask 0xffc as the Lower 2 bits indicates
+ * address space location
+ */
+ info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
+ (reg & 0xffc);
+ }
+
+ if (reg_base == 0xffffffff)
+ return 0;
+
+ rte_write32(reg_base, (uint8_t *)bp->bar0 +
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
+
+ return 0;
+}
+
static void bnxt_dev_cleanup(struct bnxt *bp)
{
bnxt_set_hwrm_link_config(bp, false);
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index f197997b89..34672dfb00 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -4788,6 +4788,10 @@ int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
err:
HWRM_UNLOCK();
+ /* Map the FW status registers */
+ if (!rc)
+ rc = bnxt_map_fw_health_status_regs(bp);
+
if (rc) {
rte_free(bp->recovery_info);
bp->recovery_info = NULL;
--
2.20.1 (Apple Git-117)
