> -----Original Message----- > From: Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco) > <[email protected]> > Sent: Tuesday, October 8, 2019 7:05 PM > To: Phil Yang (Arm Technology China) <[email protected]>; [email protected] > Cc: [email protected]; [email protected]; Honnappa Nagarahalli > <[email protected]>; Damjan Marion (damarion) > <[email protected]>; nd <[email protected]>; Gavin Hu (Arm Technology > China) <[email protected]>; nd <[email protected]> > Subject: RE: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way > barrier > > > > -----Original Message----- > > > From: dev <[email protected]> On Behalf Of Phil Yang > > > Sent: Monday, August 26, 2019 7:00 PM > > > To: [email protected]; [email protected] > > > Cc: [email protected]; [email protected]; Honnappa Nagarahalli > > > <[email protected]>; [email protected]; nd > > <[email protected]> > > > Subject: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way > > > barrier > > > > > > Using 'rte_mb' to synchronize the shared ring head/tail between > > > producer and consumer will stall the pipeline and damage performance > > > on the weak memory model platforms, such like aarch64. Meanwhile > > > update the shared ring head and tail are observable and ordered > between > > CPUs on IA. > > > > > > Optimized this full barrier with the one-way barrier can improve the > > > throughput. On aarch64 n1sdp server this patch make testpmd > throughput > > > boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain. > > > > > > Signed-off-by: Phil Yang <[email protected]> > > > Reviewed-by: Gavin Hu <[email protected]> > > The patch is looking good, but 'MEMIF_VERSION_MAJOR' in memif.h needs > to > be set to 3 as ring pointers are no longer volatile.
Updated in v2. Thanks for your comments. Thanks, Phil
