Hi Gavin, On 10/22/19 5:27 PM, Gavin Hu wrote: > Armv8's peripheral coherence order is a total order on all reads and > writes to that peripheral, that makes a compiler barrier is enough for > abstracted rte io barrier. > > For virtual PCI devices, the virtual device memory is actually normal > memory and the Hypervisor view of things takes precedence and they are > within a smp configuration and smp barriers should be used, the > relaxed io barrier for aarch64 becomes insufficient.
IIUC, this series is for performance optimization and not fixing coherency issues. Can you confirm? If that's the case, I'm afraid we'll have to postpone it to v20.02, our patch queues are already too big at that stage of the release. Maxime > Gavin Hu (3): > eal/arm64: relax the io barrier for aarch64 > net/virtio: virtual PCI requires smp barriers > crypto/virtio: virtual PCI requires smp barriers > > drivers/crypto/virtio/virtio_pci.c | 124 > ++++++++++++++++----- > drivers/net/virtio/virtio_pci.c | 124 > ++++++++++++++++----- > .../common/include/arch/arm/rte_atomic_64.h | 6 +- > 3 files changed, 191 insertions(+), 63 deletions(-) >
