> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Wednesday, November 13, 2019 22:50
> To: Xu, Rosen <rosen...@intel.com>; dev@dpdk.org
> Cc: Zhang, Tianfei <tianfei.zh...@intel.com>; Pei, Andy
> <andy....@intel.com>; Ye, Xiaolong <xiaolong...@intel.com>
> Subject: Re: [PATCH v16 10/19] raw/ifpga: add SEU error handler
>
> On 11/13/2019 7:08 AM, Rosen Xu wrote:
> > Add SEU interrupt support for FPGA.
> >
> > Signed-off-by: Tianfei zhang <tianfei.zh...@intel.com>
> > Signed-off-by: Rosen Xu <rosen...@intel.com>
> > Signed-off-by: Andy Pei <andy....@intel.com>
>
> <...>
>
> > +static int
> > +fme_err_handle_error0(struct opae_manager *mgr) {
> > + struct feature_fme_error0 fme_error0;
> > + u64 val;
> > +
> > + if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
> > + return -EINVAL;
> > +
> > + fme_error0.csr = val;
> > +
> > + if (fme_error0.fabric_err)
> > + IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
> > + else if (fme_error0.fabfifo_overflow)
> > + IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow
> error\n");
> > + else if (fme_error0.afu_acc_mode_err)
> > + IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch
> detected\n");
> > + else if (fme_error0.pcie0cdc_parity_err)
> > + IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
> > + else if (fme_error0.cvlcdc_parity_err)
> > + IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
> > + else if (fme_error0.fpgaseuerr) {
> > + fme_err_read_seu_emr(mgr);
> > + rte_panic("SEU error occurred\n");
>
> Hi Rosen, Andy,
>
> We are not allowed to call 'rte_panic()' from the drivers, can you please
> remove all instances?
Okay, fixed in v17.
